Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 179

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
the master and all other devices on the bus are configured as slaves. The master asserts the
SS pin on the selected slave. Then, the active master drives the clock and transmit data on
the SCK and MOSI pins to the SCK and MOSI pins on the slave (including those slaves
which are not enabled). The enabled slave drives data out its MISO pin to the MISO mas-
ter pin.
When the ESPI is configured as a master in a multi-master SPI system, the SS pin must be
configured as an input. The SS input signal on a device configured as a master must
remain High. If the SS signal on the active master goes Low (indicating another master is
accessing this device as a slave), a collision error flag is set in the ESPI status register. The
slave select outputs on a master in a multi-master system must come from GPIO pins.
SPI Slave Operation
The ESPI block is configured for SLAVE mode operation by setting the MMEN bit = 0 in
the ESPICTL Register and setting the
SSMD field of the ESPI mode register is set to 00 for SPI protocol mode. The
CLKPOL
MODE Register must be set to be consistent with the other SPI devices. Typically for an
SPI slave SSPO = 0.
If the slave has data to send to the master, the data must be written to the data register
before the transaction starts (first edge of SCK when SS is asserted). If the data register is
not written prior to the slave transaction, the MISO pin outputs all 1s.
Due to the delay resulting from synchronization of the SS and SCK input signals to the
internal system clock, the maximum SCK baud rate which is supported in SLAVE mode is
the system clock frequency divided by 8. This rate is controlled by the SPI master.
Figure 32 illustrates the ESPI configuration in SPI SLAVE mode.
From Master
From Master
From Master
To Master
and
WOR
Figure 32. ESPI Configured as an SPI Slave
bits in the ESPICTL Register and the NUMBITS field in the ESPI-
SS
MISO
MOSI
SCK
P R E L I M I N A R Y
Bit 7
8-bit Shift Register
SSIO
SPI Slave
bit
Z16FMC Series Motor Control MCUs
= 0
in the ESPIMODE Register. The
Bit 0
Enhanced Serial Peripheral Interface
Product Specification
Phase
,
157