Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 145

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
LIN-UART DMA Interface
LIN-UART Baud Rate Generator
UART Data Rate (bps)
Baud Rate Generator Interrupts
If the BRGCTL bit of the Multiprocessor Control Register is set (see page 132) and the
REN
LIN-UART baud rate generator reloads. This action allows the BRG to function as an
additional counter if the LIN-UART receiver functionality is not employed. The transmit-
ter is enabled in this mode.
The DMA engine is configured to move UART transmit and/or receive data. This reduces
processor overhead, especially when moving blocks of data. The DMA interface on the
LIN-UART consists of the
RxDmaAck
requests.
If transmit data is to be moved by the DMA, the transmit interrupt must be disabled in the
interrupt controller. If receive data is to be moved by the DMA, the RDAIRQ bit in the
LIN-UART Control 1 register must be set. This disables receive data interrupts when still
enabling error interrupts. The receive interrupt must be enabled in the interrupt controller
to process error condition interrupts.
The LIN-UART baud rate generator creates a lower frequency baud rate clock for data
transmission. The input to the BRG is the system clock. The LIN-UART baud rate high
and low byte registers combine to create a 16-bit baud rate divisor value (
which sets the data transmission rate (baud rate) of the LIN-UART. The LIN-UART data
rate is calculated using the following equation for normal UART operation:
The LIN-UART data rate is calculated using the following equation for LIN mode UART
operation:
UART Data Rate (bps)
When the LIN-UART is disabled, the BRG functions as a basic 16-bit timer with interrupt
on timeout. Observe the following steps to configure BRG as a timer with interrupt on
timeout:
1. Disable the LIN-UART receiver by clearing the REN bit in the LIN-UART Control 0
Register to 0 (TEN bit is asserted, transmit activity may occur).
bit of the Control 0 Register is 0, the LIN-UART receiver interrupt asserts when the
inputs. Any of the DMA channels are configured to process the UART DMA
P R E L I M I N A R Y
TxDmaReq
=
=
--------------------------------------------------------------------------------------------- -
16 UART Baud Rate Divisor Value
--------------------------------------------------------------------------------- -
UART Baud Rate Divisor Value
System Clock Frequency (Hz)

System Clock Frequency (Hz)
and
RxDmaReq
Z16FMC Series Motor Control MCUs
outputs and the
Product Specification
TxDmaAck
BRG[15:0]
LIN-UART
and
)
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