Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 217

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

I
Table 99. I
Table 100. I
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
Field
RESET
R/W
ADDR
2
C Control Register Definitions
I
I
2
2
C Data Register
C Interrupt Status Register
2
C Data Register (I2CDATA)
2
C Interrupt Status Register (I2CISTAT)
TDRE
R
7
7
1
The following section describes the I
The I
ister to transmit onto the I
Register after it is received from the I
Register File address space, but is used only to buffer incoming and outgoing data.
Writes by software to the I2CDATA Register are blocked if a slave write transaction is
underway (I
The Read-only I
current I
one or more of the
bits do not generate an interrupt but rather provide status associated with the
rupt.
2
C Data Register (see Table 99) holds the data that is to be loaded into the Shift Reg-
2
RDRF
C interrupt and provides status of the I
R
6
6
0
2
C Controller in slave mode, data being received).
2
C Interrupt Status Register (see Table 100) indicates the cause of any
TDRE
SAM
R
5
5
0
,
2
RDRF
C bus. This register also holds data that is loaded from the Shift
P R E L I M I N A R Y
,
SAM
GCA
R
4
4
0
,
FF_E240H
FF_E241H
2
2
C bus. The I
C Control registers.
ARBLST
DATA
R/W
0
,
RD
Z16FMC Series Motor Control MCUs
R
3
SPRS
3
0
2
C Controller
2
C Shift Register is not accessible in the
or
ARBLST
NCKI
R
2
2
0
.
I2C Master/Slave Controller
bits is set
When an interrupt occurs
Product Specification
SPRS
R
1
1
0
.
The
SAM
GCA
NCKI
bit inter-
and
R
0
0
0
RD
,
195