Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 203

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
4. Software responds to the TDRE interrupt by writing the first slave address byte
5. Software asserts the
6. The I
7. The I
8. When one bit of address is shifted out by the SDA signal, the Transmit interrupt
9. Software responds by writing the second byte of address into the contents of the I
10. The I
11. The I
12. The I
13. The I
14. Software responds by writing the data to be written out to the I
15. The I
16. The I
17. The I
18. If more bytes remain to be sent, return to step 14.
19. Software responds by asserting the STOP bit of the I
20. The I
(
Register.
asserts.
Data Register.
signal.
High period of SCL. The I
If the slave does not acknowledge the first address byte, the I
NCKI bit in the I
State Register. Software responds to the Not Acknowledge interrupt by setting the
STOP bit and clearing the
from the data register, sends the STOP condition on the bus and clears the
NCKI
Register (2nd address byte).
bit is sent, the Transmit interrupt asserts.
data bytes if looping) by the SDA signal.
High period of SCL. The I
If the slave does not acknowledge, see the second paragraph of step 11 above.
Transmit interrupt asserts.
11110xx0
2
2
2
2
2
2
2
2
2
2
bits. The transaction is complete (ignore the following steps).
C Controller sends the START condition to the I
C Controller loads the I
C Controller shifts the rest of the first byte of address and write bit out the SDA
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller loads the I
C Controller shifts the second address byte out the SDA signal. When the first
C Controller shifts out the rest of the second byte of slave address (or ensuing
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller shifts the data out by the SDA signal. After the first bit is sent, the
C Controller completes transmission of the data on the SDA signal.
). The least-significant bit must be 0 for the write operation.
2
C Status Register, sets the
START
P R E L I M I N A R Y
TXI
2
2
C Controller sets the ACK bit in the I
C Controller sets the ACK bit in the I
bit of the I
2
2
C Shift Register with the contents of the I
bit. The I
C Shift Register with the contents of the I
2
C Control Register.
2
C Controller flushes the second address byte
Z16FMC Series Motor Control MCUs
ACKV
bit and clears the
2
C Control Register.
2
C Slave.
I2C Master/Slave Controller
Product Specification
2
C Controller sets the
2
C Control Register.
2
2
C Status Register.
C Status Register.
ACK
bit in the I
2
2
C Data
C Data
STOP
and
2
C
2
C
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