Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 111

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Manual Off-state Control of PWM Output Channels
Deadband Insertion
Minimum PWM Pulse Width Filter
POLx causes the high-side output to start in the off-state and the low-side output to start in
the on-state.
Each PWM output is controlled directly by the modulator logic or set to the off-state. To
manually set the PWM output to the off-state, set the OUTCTL bit and the associated
OUTx
individually by channel. For example, suppressing a single output of pair allows the com-
plementary channel to continue operating. Similarly, if the outputs are operating indepen-
dently disabling one output channel has no effect on the other PWM outputs.
When the PWM outputs are configured to operate as complementary pairs, an 8-bit dead-
band value is defined in the PWM Deadband Register (PWMDB). Inserting deadband
time causes the modulator to separate the deassertion of one PWM signal from the asser-
tion of its complement. This action is essential for many motor control applications to pre-
vent simultaneous turn-on of the high-side and low-side drive transistors. The deadband
counter directly counts system clock cycles and is unaffected by PWM prescaler settings.
The width of this deadband is the number of system clock cycles specified in the <Cross-
Ref>PWM Deadband Register (PWMDB). The minimum deadband duration is zero sys-
tem clocks and the maximum time is 255 system clocks. Both PWM outputs of a
complementary pair is deasserted during the deadband period. Generation of deadband
time does not alter the PWM period but the deadband time is subtracted from the active
time of the PWM outputs. Figures 12 and 13 display the effect of deadband insertion on
the PWM output.
The PWM modulator is capable of producing pulses as narrow as a single system clock
cycle in width. The response time of external drive circuit is slower than the period of a
system clock. Therefore, a filter is implemented to enforce a minimum width pulse on the
PWM output pins. All output pulses, either High or Low, must be at least the minimum
number of PWM clock cycles (for more details, see the
86) in width as specified in the PWM Minimum Pulse Width Filter (PWMMPF) register.
If the expected pulse width is less than the threshold, the associated PWM output does not
change state until the duty cycle value has changed sufficiently to allow pulse generation
of an acceptable width. The minimum pulse width filter also accounts for the duty cycle
variation caused by the deadband insertion. The PWM output pulse is filtered even if the
programmed duty cycle is greater than the threshold but the decrease in pulse width
because of deadband insertion causes the pulse to be too narrow. The pulse width filter
value is calculated as:
bits in the PWM Output Control Register (PWMOUT). Off-state control operates
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
PWM Prescaler
Multi-Channel PWM Timer
Product Specification
section on page
89