Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 81

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Bit 7 is the Break/Abort status
In the Asynchronous mode, this bit is set when a Break se-
quence (null character plus framing error) is detected in
the receive data stream. This bit is reset when the se-
quence is terminated, leaving a single null character in the
receive FIFO. This character should be read and discard-
ed. In SDLC mode, this bit is set by the detection of an
Abort sequence (seven or more “1s”), then reset automat-
ically at the termination of the Abort sequence. In either
case, if the Break/Abort IE bit is set, an External/Status in-
terrupt is initiated. Unlike the remainder of the Exter-
nal/Status bits, both transitions are guaranteed to cause
an External/Status interrupt, even if another External/Sta-
tus interrupt is pending at the time these transitions occur.
This procedure is necessary because Abort or Break con-
ditions may not persist.
Bit 6 is the Transmit Underrun/EOM status
This bit is set by a channel or hardware reset and when the
transmitter is disabled or a Send Abort command is issued.
This bit can only be reset by the reset Tx Underrun/EOM
Latch command in WR0. When the Transmit Underrun oc-
curs, this bit is set and causes an External/Status interrupt
(if the Tx Underrun/EOM IE bit is set).
Only the 0-to-1 transition of this bit causes an interrupt.
This bit is always “1” in Asynchronous mode, unless a re-
set Tx Underrun/EOM Latch command has been errone-
ously issued. In this case, the Send Abort command can
be used to set the bit to one and at the same time cause
an External/Status interrupt.
Bit 5 is the Clear to Send pin status
If the CTS IE bit in WR15 is set, this bit indicates the state
of the /CTS pin while no interrupt is pending latches the
state of the /CTS pin and generates an External/Status in-
terrupt. Any odd number of transitions on the /CTS pin,
while another External/Status interrupt is pending, also
causes an External/Status interrupt condition. If the CTS
IE bit is reset, it merely reports the current unlatched state
of the /CTS pin.
Bit 4 is the SYNC/Hunt status
The operation of this bit is similar to that of the CTS bit, ex-
cept that the condition monitored by the bit varies depend-
ing on the mode in which the ISCC is operating.
When the XTAL oscillator option is selected in asynchro-
nous modes, this bit is forced to “0” (no External/Status in-
terrupt is generated). Selecting the XTAL oscillator in syn-
chronous or SDLC modes had no effect on the operation
of this bit.
The XTAL oscillator should not be selected in External
Sync mode.
P R E L I M I N A R Y
In Asynchronous mode, the operation of this bit is identical
to that of the CTS status bit, except that this bit reports the
state of the /SYNC pin.
In External sync mode the /SYNC pin is used by external
logic to signal character synchronization. When the Enter
Hunt Mode command is issued in External Sync mode, the
/SYNC pin must be held High by the external sync logic un-
til character synchronization is achieved. A High on the
/SYNC pin holds the Sync/Hunt bit in the reset condition.
When external synchronization is achieved, /SYNC must
be driven Low on the second rising edge of the Receive
Clock after the last rising edge of the Receive Clock on
which the last bit of the receive character was received.
Once /SYNC is forced Low, it is good practice to keep it
Low until the CPU informs the external sync logic that syn-
chronization has been lost or that a new message is about
to start. Both transitions on the /SYNC pin cause Exter-
nal/Status interrupts if the Sync/Hunt IE bit is set to “1”.
The Enter Hunt Mode command should be issued when-
ever character synchronization is lost. At the same time,
the CPU should inform the external logic that character
synchronization has been lost and that the ISCC is waiting
for /SYNC to become active.
In the Monosync and Bisync Receive modes, the
Sync/Hunt status bit is initially set to “1” by the Enter Hunt
Mode command. The Sync/Hunt bit is reset when the
ISCC established character synchronization. Both transi-
tions cause External/Status interrupts if the Sync/Hunt IE
bit is set. When the CPU detects the end of message or the
loss of character synchronization, the Enter Hunt Mode
command should be issued to set the Sync/Hunt bit and
cause an External/Status interrupt. In this mode, the
SYNC pin is an output, which goes Low every time a sync
pattern is detected in the data stream.
In the SDLC modes, the Sync/Hunt bit is initially set by the
Enter Hunt Mode command or when the receiver is dis-
abled. It is reset when the opening flag of the first frame is
detected by the ISCC. An External/Status interrupt is also
generated if the Sync/Hunt IE bit is set. Unlike the Mono-
sync and Bisync modes, once the Sync/Hunt bit is reset in
SDLC mode, it does not need to be set when the end of the
frame is detected. The ISCC automatically maintains syn-
chronization. The only way the Sync/Hunt bit can be set
again is by the Enter Hunt Mode command or by disabling
the receiver.
Z16C35ISCC™ User’s Manual
Register Descriptions
5-21
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