Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 52

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Data Communication Modes
4.4 BIT-ORIENTED SYNCHRONOUS MODE (Continued)
transmitter automatically performs zero insertion after five
consecutive ones, irrespective of character boundaries. In
turn, the receiver searches the receive data stream for five
consecutive “1s” and deletes the next bit if it is a “0”.
CRC may be used in SDLC mode but only with the CRC-
CCITT polynomial. In the SDLC Mode, the transmitter in
the SCC cell automatically inverts the CRC before trans-
mission Because of this inversion, the receiver CRC check
results in a non-zero, but fixed remainder for errorless da-
ta.
“0001110100001111” and this is the pattern automatically
checked for in the receiver in this mode. This is consistent
with bit-oriented protocols such as SDLC, HDLC, and AD-
CCP.
SDLC mode is selected by setting bit D5 of WR4 to “1” and
bits D4, D3, and D2 of WR4 to “0”. In addition, the flag se-
quence must be written to WR7. Additional control bits for
SDLC mode are located in WR10.
4.4.1 SDLC Transmit
In SDLC mode the transmitter moves characters from the
transmit buffer to the shift register, through the zero insert-
er, and out the TxD pin. The transmitter does not automat-
ically send the address byte; it merely encapsulates the
data supplied by the processor with flags and CRC. Also,
the processor must load the flag into WR7 as the ISCC
does not have a default flag pattern.
Ordinarily, a frame will be terminated by the ISCC with
CRC and a flag but the ISCC may be programmed to send
an abort and a flag in place of the CRC. This option allows
the ISCC to abort a frame transmission in progress if the
transmitter is accidentally allowed to underrun. This is con-
trolled by the Abort/Flag on Underrun bit (D2) in WR10.
When this bit is set to “1” the transmitter will send an abort
and a flag in place of the CRC when an underrun occurs.
The frame will be terminated normally, with CRC and a
flag, if this bit is set to “0”, and the Tx Underrun /EOM latch
is reset.
The ISCC is also able to send an abort by command of the
processor. The Send Abort command, issued in WR0, will
send eight consecutive “1s” and then the transmitter will
idle. The Send Abort command also empties the transmit
buffer register. Since up to five consecutive “1s” may have
been sent prior to the Send Abort command being issued,
the command will cause a sequence of from eight to thir-
teen “1s” to be transmitted (five ones of data followed by
eight ones of the abort).
After the abort when the transmitter enters the idle condi-
tion, the ISCC permits sending continuous 1’s instead of
idle flags. This option is invoked by setting the Mark/Flag
4-18
The
fixed
remainder
for
this
mode
is
idle bit (D3) in WR10 to “1”. Note that the closing flag will
be transmitted correctly even if this mode is selected.
Before a new frame is transmitted, the Mark/Flag idle bit
must be set to “0” to allow an opening flag to be transmit-
ted. The Mark/Flag Idle bit must be set to “0” before data
is written to the transmit buffer. Care must be exercised in
doing this because the continuous “1s” are transmitted,
eight at a time (as bytes) by the transmit shift register. After
setting the Mark/Flag Idle bit to “0”, the software must allow
time for eight continuous ones to have left the Transmit
Shift register before the first data byte is written to the
transmit buffer. This allows the transmitter to recognize
that the Flag Idle option has been invoked then, seeing an
empty transmit buffer, the transmitter will load the flag into
the shift register for transmission. Once the flag load has
been done, the data may be placed in the transmit buffer
without disturbing the transmission of the flag. (Note that
when using the transmitter in SDLC mode, all data passes
through the zero inserter, which adds an extra five bit times
of delay between the Transmit Shift register and the Trans-
mit Data pin.)
The number of bits per transmitted character is controlled
by bits D6 and D5 of WR5 and the way the data is format-
ted within the transmit buffer. The bits in WR5 allow the op-
tion of five, six, seven, or eight bits per character. When
“five bits per character” is selected, the data must be spe-
cially formatted before being written to the transmit buffer.
This formatting is shown in Table 4-2. In all cases the data
must be right-justified, with the unused bits being pro-
grammed as per the table (three zeros to the left of the
data followed by 1’s to the left of the zeros to complete the
byte).
An additional bit, carrying parity information, may be auto-
matically appended to every transmitted character by set-
ting bit D6 of WR4 to “1”. This bit is sent in addition to the
number of bits specified in WR4 or by the data format. The
parity sense is selected by bit D1 of WR4. Parity is not nor-
mally used in SDLC mode.
The character length may be changed on the fly, but the
desired length must be selected before the character is
loaded into the transmit shift register from the transmit
buffer. The easiest way to ensure this is to write to WR5 to
change the character length before writing the data to the
transmit buffer.
Only the CRC-CCITT polynomial may be used in SDLC
mode. This is selected by setting bit D2 in WR5 to “0”. This
bit controls the selection for both the transmitter and re-
ceiver. The initial state of the generator and checker is
controlled by bit D7 of WR10. When this bit is set to “1”,
both the generator, and checker will have an initial value of
UM011001-0601