Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 267

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
ISCC QUESTIONS AND ANSWERS
Q. Is the interrupt vector present on both the lower
A. Both halves of the AD bus are driven during an inter-
Q. In DMA mode, must the /WAIT//READY and
A. No, not exactly. The documented timing shows when
Q. Can the address and data bus be outputted before
A. No.
Q. What causes the Terminal Count to be Reset?
A. Refer to P.5-26 TM, Sec. 5.6.2, “the status in this reg-
Q. Which Rev of the SCC is in the ISCC?
A. It is the D Rev (but without the oscillator fix).
Q. Does the ISCC allow software interrupt acknowl-
A. Yes, it does. It is not required to use the /INTACK sig-
8 bits and the upper 8 bits in an interrupt cycle (See
Figure 40 of the Z16C35 CMOS ISCC Product
Spec)?
rupt acknowledge cycle by the ISCC. In fact, both
halves of the data bus are never driven individually.
/BUSACK signals be externally synchronized to
PCLK (See Figure 46 of the Z16C35 CMOS ISCC
Product Spec)?
the ISCC samples these coming back from memory.
/BUSACK is received (See Figure 46 of Z16C35
CMOS ISCC Product Spec)?
ister is automatically cleared after a Read.” In other
words the bits are Reset when you Read the contents
of the register.
edge (WR9 bit D5)?
nal of the ISCC to process interrupts. The source of the
interrupt can be determined by reading the interrupt
vector just like a normal interrupt is determined by
reading the interrupt vector (like a normal register
Read). The SCC RR2B is modified to reflect the
source. RR2A is not modified. Also, the other status
registers could be used to figure out who interrupted.
SCC interrupts can be Reset by reading RR2B if soft-
ware interrupt acknowledge is enabled (WR9 D5=1).
U
Z
C
Q
Q. Does the software interrupt acknowledge support
A. No. Unlike the SCC core, the DMA core does not sup-
Q. When the ISCC is used on a multiplexed bus, the
A. When programmed for multiplexed bus operation, sim-
Q. Can the Upper Address Strobe be defeated (to
A. No. But this is possible in the IUSC!
Q. How many clock cycles does it take to do a DMA
A. By looking at Figure 45 of Z16C35 CMOS ISCC Prod-
Q. Is there any reason why the ISCC couldn’t use pclk
A. No, as long as the required timings are met!
SER
UESTIONS AND
ILOG
ONTROLLER
DMA operation?
port this feature. The DMA has two sources of the in-
terrupt, i.e., IP and IUS bits.
ISCC does not interrupt when the SCC source in-
terrupts occur until after another Write to the ISCC.
Why?
ilar to the Z8030/Z80C30, the /AS signal is used to up-
date the interrupt status of the SCC. Consequently, if
no /AS is present, the interrupt status is not updated
until an /AS occurs. If /AS of the ISCC is tied to the /AS
of the processor, sufficient /AS signals will occur to
keep the ISCC interrupts up to date. However, if /AS is
only generated to the ISCC when it is being accessed,
any pending SCC interrupts will not assert the /INT pin
until after the /AS of an access to the part. This typical-
ly occurs when a PAL is used to generate the access
signals to the ISCC and /AS is only generated to the
ISCC when it is being accessed.
shorten the transfer cycle time)?
transfer, after BUSACK is granted?
uct Spec, it takes TS0, TS1, T0, T1, T2, T3, T4, T5,
about 8 cycles total.
twice as fast as the processor, in order to cut ac-
cess recovery times?
’
S
M
ANUAL
ISCC
A
NSWERS
™
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