Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 66

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Register Descriptions
5.4 WRITE REGISTERS (Continued)
Bit 7, 6, and 5 are not used in the ISCC. These bits were
used in the SCC cell to control the action of the
/WAIT//REQUEST pin but they have no function in the
ISCC since this pin does not exist in this device. For code
compatibility purposes, there is no restriction on how these
bits are programmed.
Bit 4 and 3 specify the various character-available condi-
tions that may cause interrupt requests.
Bit combination 00 programs Receive Interrupts Disabled.
This mode prevents the receiver from requesting an inter-
rupt and is normally used in a polled environment where ei-
ther the status bits in RR0 or the modified vector in RR2
(Channel B) can be monitored to initiate a service routine.
Although the receiver interrupts are disabled, a special
condition can still provide a unique vector status in RR2.
Bit combination 01 programs Receive Interrupt on First
Character or Special Condition. The receiver requests an
interrupt in this mode on the first available character (or
stored FIFO character) or on a special condition. Sync
characters to be stripped from the message stream do not
cause interrupts.
Special receive conditions are: receiver overrun, framing
error, end of frame, or parity error (if selected). If a special
receive condition occurs, the data containing the error is
5-6
Write Register 1
D7
D6
D5 D4 D3 D2 D1 D0
0
0
1
1
0
1
0
1
Figure 5-3. Write Register 1
Rx Int Disable
Rx Int On First Character or Special Condition
Int On All Rx Characters or Special Condition
Rx Int On Special Condition Only
P R E L I M I N A R Y
stored in the receive FIFO until an Error Reset command
is issued by the CPU.
This mode is usually selected when a Block Transfer mode
is used. In this interrupt mode, a pending special receive
condition remains set until either an Error Reset Com-
mand, a channel or hardware reset, or until receive inter-
rupts are disabled.
The Receive Interrupt on First Character or Special Condi-
tion mode can be re-enabled by the Enable Rx Interrupt on
Next Character command in WR0.
Bit combination 10 programs Interrupt on All Receive
Characters or Special Condition. This mode allows an in-
terrupt for every character received (or character in the re-
ceive FIFO) and provides a unique vector when a special
condition exists. The Receiver Overrun bit and the Parity
Error bit in RR1 are two special conditions that are latched.
These two bits must be reset by the Error Reset command.
Receiver overrun is always a special receive condition,
and parity can be programmed to be a special condition.
Data characters with special receive conditions are not
held in the receive FIFO in the Interrupt On All Receive
Characters or Special Conditions Mode as they are in the
other receive interrupt modes.
Not Used
Not Used
Not Used
Ext Int Enable
Tx Int Enable
Parity Is Special Condition
UM011001-0601