Z16C3516VSG Zilog, Z16C3516VSG Datasheet
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Z16C3516VSG Summary of contents
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... In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. The standard Zilog interrupt daisy chain is supported for in- terrupt hierarchy control. Internally, the SCC cell has high- er interrupt priority than the DMA cell. ...
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Z16C35 ISCC™ User’s Manual General Description 1.1 INTRODUCTION (Continued) 1-2 Figure 1-1. Block Diagram UM011001-0601 ...
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... Low Power CMOS Technology Two General-Purpose SCC Channels, Four DMA Channels; and Universal Bus Interface Unit Software Compatible to the Zilog CMOS SCC Four DMA Channels; Two Transmit and Two Receive Channels to and from the SCC Four Gigabyte Address Range per DMA Channel ...
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Z16C35 ISCC™ User’s Manual General Description 1.2 FEATURES (Continued) 1-4 Figure 1-2. Pin Functions UM011001-0601 ...
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IEO 11 /INT 12 /SYNCA 13 /RTxCA 14 GND 15 VCC 16 AD0 17 AD1 AD2 18 AD3 19 AD4 20 AD5 21 AD6 22 AD7 23 GND 24 VCC 25 N ...
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Z16C35 ISCC™ User’s Manual General Description 1.3 PIN DESCRIPTION The following section describes the Z16C35 pin functions. Figures 1-2 and 1-3 detail the respective pin functions and pin assignments. All references to DMA are internal. /CTSA, /CTSB. Clear To Send ...
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In SDLC mode, the pins act as outputs and are valid on receipt of a flag. The output is active for one receive clock period (refer to Chap- ter 4). TxDA, TxDB. Transmit Data (outputs, active ...
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Z16C35 ISCC™ User’s Manual General Description 1.3 PIN DESCRIPTION (Continued) When the ISCC is the bus master (the DMA cell has taken control of the bus), the /Wait//RDY signal functions as a /WAIT or /READY input. Slow memories and peripheral ...
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INTRODUCTION This chapter details the interfacing of the 16C35 ISCC to a system. Covered in this chapter is a description of the Bus Interface Unit (BIU) and information about the ISCC in non- multiplexed and multiplexed bus operation. The ...
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Z16C35 ISCC™ User’s Manual Interfacing the ISCC™ 2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION (Continued) on the accessing of the internal registers. Register access is made solely through the latched address. However, the pointer in the DMA Channel Command/Address Register functions ...
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Table 2-1. ISCC Bus Access Summary Byte Swap Lower Process Enable Select 8 Bits Read X X data Write X X data read DMA Write 0 X data DMA Read 0 X data read DMA Write 1 X data DMA ...
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Z16C35 ISCC™ User’s Manual Interfacing the ISCC™ 2.3 I/O INTERFACE CAPABILITIES (Continued) subsequent peripherals. Internally, the SCC cell is higher priority than the DMA cell. An IUS bit is set during an Inter- rupt Acknowledge cycle if there are no ...
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REGISTER ACCESS ISCC registers may be accessed explicitly, directly or indi- rectly. Explicit addressing occurs only for three registers in the ISCC: these are the Bus Configuration Register (for the first write after a hardware reset), the RDR (Receive ...
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Z16C35 ISCC™ User’s Manual Interfacing the ISCC™ 2.4 REGISTER ACCESS (Continued) Table 2-3. SCC Cell Address Map, Multiplexed Bus Mode, Shift Right Address AD4-AD0 Write 00000 WR0B 00001 WR0A 00010 WR1B 00011 WR1A 00100 WR2 00101 WR2 00110 WR3B 00111 ...
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Table 2-4. SCC Cell Register Address Map Using Pointer (Non-multiplexed Bus Mode) Using Null Command Address A1/A// Register 0 000 WR0B 0 001 WR1B 0 010 0 011 WR3B 0 100 WR4B 0 101 WR5B 0 110 ...
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Z16C35 ISCC™ User’s Manual Interfacing the ISCC™ 2.4 REGISTER ACCESS (Continued) Address* Name xxxxx BCR 00000 CCAR 00000 DSR 00001 ICR 00010 IVR 00011 ICSR 00011 ISR 00100 DER 00101 DCR 00110 00111 01000 RDCRA 01001 RDCRA 01010 TDCRA 01011 ...
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DMA Register Access, Non-Multiplexed Bus Mode The registers in the DMA cell in the non-multiplexed bus mode are accessed in a two-step process, using a Regis- ter Pointer to perform the addressing. To access a partic- ular register, the ...
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UM011001-0601 ...
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INTRODUCTION The most important feature of the ISCC other than SCC cell is the integrated, four channel DMA controller the original SCC, the serial channels of the ISCC are support- 3.2 DMA The ISCC™ contains four independent ...
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Z16C35ISCC™ User’s Manual ISCC™ DMA and Ancillary Support Circuitry Receive Character Available bit in the SCC cell in Read Register 0. The SCC cell will not generate a DMA request in the case of a special receive condition in the ...
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The BRG is enabled while bit DO of WR14 is set to 1 and disabled while this bit is set to 0 ...
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Z16C35ISCC™ User’s Manual ISCC™ DMA and Ancillary Support Circuitry 3.3 BAUD RATE GENERATOR (Continued) The formulas relating the baud rate to the time-constant and vice versa are shown below. The clock mode in the formula is the ratio of the ...
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DATA ENCODING/DECODING The ISCC provides four different data encoding methods, selected by bits D6 and D5 in WR10. An example of these four encoding methods is shown in Figure 3-3. Any encoding method may be used in any X1 ...
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Z16C35ISCC™ User’s Manual ISCC™ DMA and Ancillary Support Circuitry 3.5 DIGITAL PHASE-LOCKED LOOP (DPLL) Each channel of the SCC cell contains a digital phase- locked loop that can be used to recover clock information from a data stream with NRZI, ...
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In the NRZI mode, the DPLL clock must be 32 times the data rate. In this mode, the transmit and receive clock out- puts of the DPLL are identical, and the clocks are phased so that the receiver samples the ...
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Z16C35ISCC™ User’s Manual ISCC™ DMA and Ancillary Support Circuitry 3.5 DIGITAL PHASE-LOCKED LOOP (DPLL) (Continued) Receive Data DPLL Output Correction + Windows Count Length Figure 3-6. DPLL Operating Example (NRZI Mode) 3.5.2 DPLL ...
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If the transition marking a bit cell boundary occurs between the middle of count 16 and the middle of count 19, the DPLL is sampling the data too early in the bit cell. In response to this, the DPLL ...
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Z16C35ISCC™ User’s Manual ISCC™ DMA and Ancillary Support Circuitry 3.5 DIGITAL PHASE-LOCKED LOOP (DPLL) (Continued) NRZ Transmit Clock Transmit Clock NRZ 3- Figure 3-8. Encoding Manchester Data 3 5 Manchester 4 2 ...
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CLOCK SELECTION The ISCC can select several clock sources for internal and external use. Write Register 11 is the Clock Mode Control register for both the receive and transmit clocks. It deter- mines the type of signal on the ...
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Z16C35ISCC™ User’s Manual ISCC™ DMA and Ancillary Support Circuitry Selection of the clocking options may be done anywhere in the initialization sequence, but the final values must be se- lected before the receiver, transmitter, baud rate genera- tor, or DPLL ...
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WR11 WR14 Figure 3-10b. Async Transmission, 1x Clock Rate, NRZ Data Encoding UM011001-0601 /TRxC Out = BRG Output /TRxC Pin = Output Pin Tx ...
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Z16C35ISCC™ User’s Manual ISCC™ DMA and Ancillary Support Circuitry External Crystal Figure 3-10c. Asynchronous Transmission, 1x Clock Rate, FM Data Encoding Figure 3-10 shows three examples of clock sources and selection. Part (a) of the figure shows the clock set ...
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INTRODUCTION The ISCC™ provides two independent full-duplex chan- nels programmable for use in any common asynchronous or synchronous data communication protocols. The data communication protocols handled by the SCC cell within the ISCC are: Asynchronous Mode Character-Oriented Mode Monosynchronous ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.1 INTRODUCTION (Continued) Internal Data Bus WR7 Sync WR6 Sync Register Register 20-Bit Transmit SDLC Zero Insert (5-Bits) CRC SDLC CRC Generator If asynchronous data is processed, WR6 and WR7 are not used and ...
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WR13 Upper Byte Time Constant BR 16-Bit Down Counter Generator Input RxD 1-Bit DPLL UM011001-0601 WR12 Lower Byte Frame Time Constant Status FIFO BR 2 Generator Output 14-Bit Counter Sync Register & Zero Delete Internal MUX TxD ...
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Z16C35ISCC™ User’s Manual Data Communication Modes Incoming data is routed through one of several paths de- pending on the mode and character length. In Asynchro- nous mode, serial data enters the 3-bit delay if the charac- ter length of seven ...
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Data field - typically 5-8 bits wide. 3. Parity bit - optional, provides mechanism for checking character validity, transmitter and receiver agree that: 4. Data + Parity bit contains odd number of 1s (odd parity) or Data + Parity ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.2 ASYNCHRONOUS MODE (Continued) The /CTS pin is ordinarily a simple input to the CTS bit in RR0. However, if Auto Enables mode is selected this pin becomes an enable for the transmitter. That ...
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Switch bounce may cause multiple breaks, recognized by the ISCC to be addi- tional characters assembled in the receive data FIFO. It may also cause a receive overrun condition being latched. Received characters are assembled, ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) Modem Clock Bit Bit State Data LSB Start and stop bits are not required in synchronous modes. All bits are used to transmit data. This eliminates the “waste” characteristic ...
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Table 4-5. Registers Used in Character-oriented Modes Register Bit No Description WR4 3 (=0) Select sync mode 2 (=0) 4 (=0) Select monosync mode 5 (=0) (8-bit sync character) 4 (=1) Select bisync mode 5 (=0) (16-bit sync character) 4 ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) transmission will be completed, but the remaining bits will come from the SYNC registers rather than the remainder of the CRC. There are two modem control signals associated with ...
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Write Register 6 D7 Sync5 Sync7 Sync6 Sync5 Sync1 Sync0 Sync5 Sync7 Sync6 Sync3 Sync2 Sync1 ADR5 ADR7 ADR6 ADR5 ADR7 ADR6 Sync7 Sync6 Sync5 Sync4 Sync15 Sync14 Sync11 Sync10 0 1 For those applications requiring any other sync character ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) /RTxC PCLK /SYNC It is sometimes desirable to prevent sync characters from entering the receive data FIFO. This function is available in the ISCC by setting the Sync Character ...
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Change from Five to Eight Change from Eight to Five Either of two CRC polynomials may be used in synchro- nous modes, selected by bit D2 in WR5. If this bit is set to “1”, the CRC-16 polynomial is used, ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued) processor reads B and enables CRC. At the end of this eight-bit time the 8-bit delay and the receive shift register. 3. Character ...
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Table 4-8. Enabling and Disabling CRC on the Fly (Sync) (Data1) (Data2) Note: No CRC Calculation on "D" Direction of Data Stage Coming into SCC ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued two modem control signals associated with the re- ceiver are available in synchronous modes: DTR/REQ and DCD. The /DTR//REQ pin carries the inverted state of the DTR ...
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A specific sequence of operations must be followed to syn- chronize the transmitter to the receiver. Both the receiver and transmitter must have been initialized for operation in Synchronous mode sometime in the past, although this ini- tialization need not ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.4 BIT-ORIENTED SYNCHRONOUS MODE (Continued) transmitter automatically performs zero insertion after five consecutive ones, irrespective of character boundaries. In turn, the receiver searches the receive data stream for five consecutive “1s” and deletes the ...
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The ISCC does not automatically preset the CRC genera- tor so this must be done in software. This is accomplished by issuing the ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.4 BIT-ORIENTED SYNCHRONOUS MODE (Continued) 4.4.2 SDLC Receive The receiver in the ISCC™ always searches the receive data stream for flag characters in SDLC mode. Ordinarily, the receiver transfers all received data between flags ...
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Change from Five to Eight Change from Eight to Five Most bit-oriented protocols allow an arbitrary number of bits between opening and closing flags. The ISCC allows for this by providing three bits of Residue Code in RR1 that indicates ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.4 BIT-ORIENTED SYNCHRONOUS MODE (Continued example of how the codes are interpreted, consider the case of eight bits per character and a residue code of 101. The number of valid bits for ...
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The /DTR//REQ pin carries inverted state of the DTR bit (D7) in WR5 unless this pin has been programmed to carry a DMA Request signal. The /DCD pin is ordinarily a simple input to the DCD bit in RR0. However, ...
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Z16C35ISCC™ User’s Manual Data Communication Modes 4.4 BIT-ORIENTED SYNCHRONOUS MODE (Continued) EOP so that it can go on loop. While waiting for the EOP, the ISCC ties TxD to RxD with only the internal gate delays in the signal path. ...
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WR5. At this point the other registers should be initialized as necessary, as shown in Table 4-14.. Table 4-14. SDLC Loop Mode initialization Register Bit No Description WR4 5-4 Select SDLC mode WR10 7 Select CRC preset value 3 Select ...
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Z16C35ISCC™ User’s Manual Data Communication Modes should not be set to “0” until the last frame is being sent. If this bit is not set to “0” before the end of a frame, the trans- mitter will send Flags until ...
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INTRODUCTION This section describes the function of the various bits in the registers of the device. Throughout this section the follow- ing conventions will be used: Control bits may be written and read by the CPU and will not ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.2 REGISTER DESCRIPTIONS (Continued) 5.2.2 Read Registers, SCC Cell Four read registers indicate status information, two are for baud rate generation, and one for the receive buffer. In ad- dition, there are two read registers ...
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WRITE REGISTERS The following sections describe WR registers in detail. 5.4.1 Write Register 0 (Command Register) WR0 is the command register and the CRC reset code register. WR0 takes on slightly different forms depending upon whether the ISCC is ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.4 WRITE REGISTERS (Continued) The following bit description for WR0 is identical for both versions except where specified. Bits D7 and D6 are the CRC Reset Codes 1 and 0. Bit combination ...
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Bit combination 110 is the Error Reset Command This command resets the error bits in RR1. If interrupt on first Rx Character or interrupt on Special Condition modes are selected and a special condition exists, the data with the special ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.4 WRITE REGISTERS (Continued) Write Register Bit 7, 6, and 5 are not used in the ISCC. These bits were used in the SCC cell to ...
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Bit combination 11 programs Receive Interrupt on Special Condition. This mode allows the receiver to interrupt only on characters with a special receive condition. When an in- terrupt occurs, the data containing the error is held in the receive FIFO ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.4 WRITE REGISTERS (Continued) 5.4.4 Write Register 3 (Receive Parameters and Control) This register contains the control bits and parameters for the receiver logic as illustrated in Figure 5-5. Write Register ...
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Bit 3 is the Receiver CRC Enable This bit is used to initiate CRC calculation at the beginning of the last byte transferred from the Receiver Shift register to the receive FIFO. This operation occurs independently of the number of ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.4 WRITE REGISTERS (Continued) Bit combination 01 selects the 16X Mode. The clock rate is 16 times the data rate. In External Sync mode, this bit com- bination specifies that only the /SYNC pin can ...
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Write Register 5 (Transmit Parameter and Controls) WR5 contains control bits that affect the operation of the transmitter. B2 affects both the transmitter and the receiv- er. Bit positions for WR5 are shown in Figure 5-7. Write Register 5 ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.4 WRITE REGISTERS (Continued) 5.4.7 Write Register 6 (Sync Characters or SDLC Address Field) WR6 is programmed to contain the transmit sync charac- ter in the Monosync mode, the first byte of a 16-bit sync ...
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Write Register Sync5 Sync7 Sync6 Sync3 Sync5 Sync4 Sync13 Sync15 Sync14 Sync9 Sync11 Sync10 5.4.9 Write Register 8 (Transmit Buffer) WR8 is the transmit buffer register. 5.4.10 Write Register 9 (Master Interrupt Control) WR9 ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.4 WRITE REGISTERS (Continued) Bit 4 is the Status High//Status Low control bit This bit controls which vector bits the SCC cell will modify to indicate status. When set to “1,” the SCC cell modifies ...
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Table 5-8. Data Encoding Bit 6 Bit 5 Encoding 0 0 NRZ 0 1 NRZI 1 0 FM1 (transition = FM0 (transition = 0) Data NRZ NRZ1 FM1 FM0 Manchester Figure 5-12. NRZ (NRZI), ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.4 WRITE REGISTERS (Continued) In synchronous modes, the ISCC uses this bit, along with the Go Active On Poll bit, to synchronize the transmitter to the receiver. The receiver should not be enabled until after ...
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Table 5-9. Receive Clock Source Bit 6 Bit 5 Receive Clock 0 0 RTxC Pin 0 1 TRxC Pin Output 1 1 DPLL Output Bits 4 and 3 are the Transmit Clock select bits 1 and 0 ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.4 WRITE REGISTERS (Continued) 5.4.14 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) WR13 contains the upper byte of the time constant for the baud rate generator. Bit positions for WR13 are ...
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Bit combination 010 is the Reset Clock Missing Command. Issuing this command disables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state. Bit combination 001 is the Disable DPLL Command. Issu- ing this ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.5 READ REGISTERS (Continued) Write Register Figure 5-17. Write Register 15 Bit 7 is the Break/Abort Interrupt Enable If this bit is set to “1,” a ...
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Bit 7 is the Break/Abort status In the Asynchronous mode, this bit is set when a Break se- quence (null character plus framing error) is detected in the receive data stream. This bit is reset when the se- quence is ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.5 READ REGISTERS (Continued) Bit 3 is the Data Carrier Detect status If the DCD IE bit in WR15 is set, this bit indicates the state of the DCD pin the last time the Enabled ...
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Bit 5 is the Receiver Overrun Error status This bit indicates that the receive FIFO has overflowed. Only the character that has been written over is flagged with this error, and when the character is read, the Error condition is ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.5 READ REGISTERS (Continued) 5.5.4 Read Register 3 RR3 is the interrupt Pending register. The status of each of the interrupt Pending bits in the SCC cell is reported in this register. This register exists ...
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Read Register 13 RR13 returns the value stored in WR13, the upper byte of the time constant for the baud rate generator. Figure 5-24 shows the bit positions for RR13. Read Register ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.6 DMA CELL REGISTER DESCRIPTIONS (Continued) Bit combination 110 is the command to enable the Trans- mitter A channel DMA. The DMA operation is not triggered by this command. Bit combination 111 is the command ...
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Bit 5 selects the no vector option. With this bit set, the DMA cell does not return an interrupt vector to the CPU. During the interrupt acknowledge cycle when the interrupt vector is requested, the ISCC will not drive the ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.6 DMA CELL REGISTER DESCRIPTIONS (Continued) Bit combination 001 resets the Interrupt Pending (IP) bit in the selected DMA channel(s). Bit combination 010 resets the Interrupt Under Service (IUS) bit in the selected DMA channel(s). ...
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DMA Enable Register This register controls the enabling of the DMA channels and contains the enables for the DMA Abort Interrupt con- ditions. The bit positions for this register are shown in Fig- ure 5-32. Address: 00100 D7 D6 ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.6 DMA CELL REGISTER DESCRIPTIONS (Continued) Table 5-15. DMA Priority D5 D4 DMA Priority A/Tx A/Rx B/ B/Tx B/Rx A/ A/Rx B/Tx A/Tx B ...
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Transmit DMA Count Registers A, B There are two sets of Transmit DMA Count Registers, one set for Transmit DMA Channel A and one set for Transmit DMA Channel B. Each register set contains two registers, Address: 01010 (Low ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.6 DMA CELL REGISTER DESCRIPTIONS (Continued) 5.6.11 Receive DMA Address Registers A, B There are two sets of Receive DMA Address Registers, one set for Receive DMA Channel A and one set for Re- ceive ...
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Address: 11000 (Bits 0- Address: 11010 (Bits 16-23 Figure 5-36. Receive DMA Address Registers (Continued) 5.6.12 Transmit DMA Address Registers A, B There are ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.6 DMA CELL REGISTER DESCRIPTIONS (Continued) Address: 10100 (Bits 0- (A) Address: 10110 (Bits 16-23 (C) 5-34 Address: 10101 ...
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Address: 11100 (Bits 0- (E) Address: 11110 (Bits 16-23 (G) Figure 5-38. Transmit DMA Address Registers (Continued) UM011001-0601 Address: 11101 (Bits 8-15 ...
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Z16C35ISCC™ User’s Manual Register Descriptions 5.6 DMA CELL REGISTER DESCRIPTIONS (Continued) 5.6.13 Bus Configuration Register The first write to the ISCC after a hardware reset is always to the Bus Configuration Register. The register is shown in Figure 5-38. The ...
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... The hardware interface consists of three basic groups of signals; data bus, system control, and interrupt control, described below. For more detailed signal information, refer to Zilog’s DataBook, Universal Peripherals. Data Bus Signals D7-D0. Data Bus (bidirectional tri-state). This bus transfers data between the CPU and the peripherals. ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family CPU HARDWARE INTERFACING (Continued) Z80 ® Interrupt Daisy-Chain Operation In the Z80 peripherals, both the IP and IUS bits control the IEO line and the lower portion of the ...
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Write Cycle Timing Figure 2 illustrates the Z8500 Write cycle timing. All register addresses and /INTACK must remain stable throughout the cycle. If /CE goes active after /WR goes Figure 2. Z8500 Peripheral I/O Write Cycle Timing UM011001-0601 Interfacing Z80 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family PERIPHERAL INTERRUPT OPERATION Understanding peripheral interrupt operation requires a basic knowledge of the Interrupt Pending (IP) and Interrupt Under Service (IUS) bits in relation to the daisy chain. Both ...
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INPUT/OUTPUT CYCLES Although Z8500 peripherals are designed universal as possible, certain timing parameters differ from the standard Z80 timing. The following sections discuss the I/O interface for each of the Z80 CPUs and the Z8500 peripherals. Figure ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family INPUT/OUTPUT CYCLES (Continued) Worst Case 6. TsA(WR) Address to /WR to Low Setup 1. TsA(RD) Address to /RD Low Setup 2. TdA(DR) Address to Read Data Valid TsCEI(WR) /CE ...
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Figure 4. Z80A CPU to Z8500 Peripheral Minimum I/O Cycle Timing UM011001-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-7 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Z80B CPU TO Z8500A PERIPHERALS No additional Wait states are necessary during I/O cycles, although Wait states can be inserted to compensate for any systems delays. Although the Z80B ...
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Worst Case 6. TsA(WR) Address to /WR Low Setup 1. TsA(RD) Address to /RD Low Setup 2. TdA(DR) Address to Read Data Valid TsCE1(WR) /CE Low to /WR Low Setup TsCE1(RD) /CE Low to /RD Low Setup 4. TwRD1 /RD ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Z90H CPU TO Z8500 PERIPHERALS During an I/O Read cycle, there are three Z8500 parameters that must be satisfied. Depending upon the loading characteristics of the /RD signal, the ...
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Figure 6. Z80H CPU to Z8500 Peripheral Minimum I/O Cycle Timing UM011001-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-11 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Z80H CPU TO Z8500A PERIPHERALS During an I/O Read cycle, there are three Z8500A parameters that must be satisfied. Depending upon the loading characteristics of the /RD signal, the ...
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Figure 7. Z80H CPU to Z8500A Peripheral Minimum I/O Cycle Timing UM011001-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-13 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Z80H CPU TO Z8500A PERIPHERALS (Continued) Z80H Z8500A Parameter Equation TsD(Cf) 4TcC+TwCh-TdCr(A)-TdA(DR) /RS - delayed 2TcC+TwCh-TdRD(DR) 6-14 Figure 8. Delaying /RD or /WR Table 14. Parameter Equations Value Units ...
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INTERRUPT ACKNOWLEDGE CYCLES The primary timing differences between the Z80 CPUs and Z8500 peripherals occur in the Interrupt Acknowledge cycle. The Z8500 timing parameters that are significant during Interrupt Acknowledge cycles are listed in Table 16, while the Z80 parameters ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family EXTERNAL INTERFACE LOGIC (Continued) Figure 9. Z80A/Z80B CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic During I/O and normal memory access cycles, the Shift registers remains cleared because the ...
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Figure 10. Z80A/Z80B CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Timing Z8500/Z8500A Peripherals Figure 11 depicts logic that can be used in interfacing the Z80H CPU to the Z8500/Z8500A peripherals. This logic is the same as that shown in Figure ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family EXTERNAL INTERFACE LOGIC (Continued) Figure 11. Z80H to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic During RETI cycles, the IEO line from the Z8500 peripherals does not change state as ...
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Figure 12. Z80H CPU to Z8500 Peripheral Interrupt Acknowledge Interface Timing Figure 13. Z80H CPU to Z8500A Peripheral Interrupt Acknowledge Interface Timing UM011001-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-19 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family EXTERNAL INTERFACE LOGIC (Continued) Figure 14. Z80 and Z8500 Peripheral Interrupt Acknowledge Interface Logic 6-20 UM011001-0601 ...
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Figure 15. Z80 and Z8500 Peripheral Interrupt Acknowledge Interface Timing UM011001-0601 ® Interfacing Z80 CPUs to the Z8500 Peripheral Family Application Note 6 6-21 ...
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Application Note ® Interfacing Z80 CPUs to the Z8500 Peripheral Family SOFTWARE CONSIDERATIONS - POLLED OPERATION There are several options available for servicing interrupts on the Z8500 peripherals. Since the vector of IP registers can be read at any time, ...
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... Because the CIO can be used in a polled interrupt environment, the /INT pin is connected to the Figure 16. Z80 to Z8500 Simple System Mode 1 Interrupt or Non-Interrupt Structure Additional Information in Zilog Publications: The Z80 Family User’s Manual includes technical information on the Z80 CPU, DMA, PIO, CTC, and SIO. ...
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UM011001-0601 ...
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... The SCC is the ideal device for this purpose. Zilog’s SCC is the multi-protocol (@ 10 MHz) universal serial communication controller which supports most serial communication applications including Monosync, Bisync and SDLC at 2.5 Mbits/sec speeds. Further, the wide acceptance of this device by the market ensures “ ...
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Application Note The Z180™ Interfaced with the SCC at MHZ INTERFACES The following subsections explain the interfaces between the: Z180 and Memory Z180 and I/O Z180 and SCC Basic goals of this system design are: System clock ...
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Table 1. Z8018010 Timing Parameters for Opcode Fetch Cycle (Worst Case: Z180 10 MHz) No Symbol 1 tcyc 2 tCHW 3 tCLW 4 tcf 6 tAD 8 tMED1 9 tRDD1 11 tAH 12 tMED2 15 tDRS 16 tDRH 22 tWRD1 ...
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Application Note The Z180™ Interfaced with the SCC at MHZ EPROM INTERFACE During an Opcode fetch cycle, data sampling of the bus is on the rising PHI clock edge of T3 and on the falling edge of T3 during a ...
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With this scheme, you can get the highest performance with moderate cost. SRAM Write Cycle. During a Z180 memory write cycle, the Z180 write data is stable before the falling edge of /WR Ø Address /MREQ /WR ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) A9 A18 A17 A16 A15 /RD /MREQ /WR * /RD to /OE Pin of 27C256 and 55257 /WR To /WE Pin of 55257 /USRRAM /IORQ A15 /USRROM 7-6 HCT138 ...
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FFFFFH S-RAM Image F8000H EP-ROM Image F0000H S-RAM Image 28000H /EP-ROM Image 20000H S-RAM Image 18000H EP-ROM Image 10000H 256K SRAM 08000H EP-ROM 27C256 00000H Figure 5. Physical Memory Address Map UM011001-0601 The Z180™ Interfaced with the SCC at MHZ ...
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Application Note The Z180™ Interfaced with the SCC at MHZ Z180 TO I/O INTERFACE The Z180 I/O read/write cycle is similar to the Z80 CPU if you clear the /IOC bit in the OMCR register to 0 (Figures 7 Ø ...
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Table 5. Z8018010 Timing Parameters for I/O Cycle (Worst Case) No Symbol 1 tcyc 2 tCHW 3 tCLW 4 tcf 6 tAD 9 tRDD1 11 tAH 13 tRDD2 15 tDRS 16 tDRH 21 tWDZ 22 tWRD1 23 tWDD 24 ...
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... CPU Hardware Interfacing The hardware interface has three basic groups of signals: Data bus, system control, and interrupt control. For more detailed signal information, refer to Zilog’s Technical Manuals, and Product Specifications for each device. Data Bus Signals D7-D0. Data bus (Bidirectional, tri-state). This bus transfers data between the Z180 and SCC ...
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Address /INTACK /CE /RD D7-D0 Write Cycle Timing Figure 11 illustrates the SCC Write cycle timing. All register addresses and /INTACK are stable throughout the cycle. The timing specification of the SCC requires that the Address /INTACK /CE /WR D7-D0 ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) SCC Interrupt Operation Understanding SCC interrupt operations requires a basic knowledge of the Interrupt Pending (IP) and Interrupt Under Service (IUS) bits in relation to the daisy chain. The ...
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Interrupt Condition IP Set IEI High? INT Active /INTACK * IEI * /RD The SCC uses /INTACK (Interrupt Acknowledge) for recognition of an interrupt acknowledge cycle. This pin, used with /RD, allows the SCC to gate its interrupt vector onto ...
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Application Note The Z180™ Interfaced with the SCC at MHZ INPUT/OUTPUT CYCLES Although the SCC is a universal design, certain timing parameters differ from the Z180 timing. The following subsections discuss the I/O interface for the Z180 MPU and SCC. ...
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Table 8. Parameter Equations Worst Case (Without Delay Signals - No Wait State) SCC Z180 Parameters Equation TsA(RD) tcyc-tAD+tRDD1 TdA(DR) 3tcyc+tCHW+tcf-tAD-tDRS TdRDf(DR) 2tcyc+tCHW+tcf-tRDD1-tDRS TwRDI 2tcyc+tCHW+tcf-tDRS+tRDD2 TsA(WR) tcyc-tAD+tWRD1 TsDW(WR) tWDS TwWRI tWRP Z180 SCC Parameters Equation tDRS Address 3tcyc+tCHW-tAD-TdA(DR) RD 2tcyc+tCHW-tRDD1-TdRD(DR) ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) /CSSCC /WR HCT74 D CK Ø /RD /RESET /MREQ /M1 4.7K Internal /WAIT Input This circuit works when [(Lower HCT164’s CLK If you are running your system slower than ...
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Table 10. 10 MHz SCC Timing Parameters for Interrupt Acknowledge Cycle No Symbol 13 TsIAi(RD) 14 ThIA(RD) 15 ThIA(PC) 38 TwRDA 39 TwRDA 40 TdRDA(DR) 41 TsIEI(RDA) 42 ThIEI(RDA) 43 TdIEI(IEO) Table 11. Z180 Timing Parameters Interrupt Acknowledge Cycles (Worst ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued Address 6 /IORQ /SCCSEL HC74 /Q HCT164 /CLR HCT164 CLK 10 ns max HCT164 Q0 HCT164 Q1 /RD (or, /WR) RD* Q1 *SCCSEL /SCCRD /[(RD* /Q1* SCCSEL) ...
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The primary chip in this logic is the Shift register (HCT164), which generates /INTACK, /SCCRD and /WAIT. During I/O and normal memory access cycles, the Shift Register (HCT164) remains cleared because the /M1 signal is inactive during the opcode fetch ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) 7-20 Figure 16a. ELPD Circuit Implementation UM011001-0601 ...
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UM011001-0601 Figure 16b. ELPD Circuit Implementation Application Note The Z180™ Interfaced with the SCC at MHZ 7 7-21 ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) System Checkout After completion of the board (PC board or wire wrapped board, etc.), the following methods verify that the board is working. Software Considerations Based on the previous ...
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Table 12. SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interrupt register returns status info: ;* Bit D0: current /cts stat ;* D1set: /cts int received ;* .z800 ;Read in Z180 register names and *include ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 12. SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interrupt) (Continued) ;external/status interrupt service routine ext_stat: ld a,10h out in and rra rra rra rra ...
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Table 13 shows a “macro” to enable the Z180 to use the Z80 Assembler, as well as register definitions. There is one good test to ensure proper function. Generate a data transfer between the Z180/SCC using the Z180 on- Table ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 13. Program Example – Z180 CPU Macro Instructions (Continued) bcr1l: equ 2eh bcr1h: equ 2fh dstat: equ 30h dmode: equ 31h dcntl: equ 32h ;System Control Registers il: ...
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Table 13. Program Example – Z180 CPU Macro Instructions (Continued) db 10000011B endm otimr macro db 11101101B db 10010011B endm otdm macro db 11101101B db 10001011B endm otdmr macro db 11101101B db 10011011B endm tstio macro ?p db 11101101B db ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 14 lists a program example for the Z180/SCC DMA transfer test. Table 14. Test Program – Z180/SCC DMA Transfer ; ;* Test program for 180 DMA/SCC ;* ;* ...
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Table 14. Test Program – Z180/SCC DMA Transfer (Continued) loop: chkloop: ld bad_data: good: enddma: ; fill_mem: l fill_loop: fill_00: fill_00l: UM011001-0601 call initdma ld b,0 ld a,00h out (scc_data),a ld a,11001100b out0 (dstat),a ld a,05h out (scc_cont),a ld a,01101000b ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 14. Test Program – Z180/SCC DMA Transfer (Continued) initscc: init0: ;initialize z180’s scc ; initdma: txend: rxend: ;initialization data table for scc ;table format - register number, then ...
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Table 14. Test Program – Z180/SCC DMA Transfer (Continued) UM011001-0601 db 01h db 01100000b db 02h db 00h db 03h db 11000000b db 05h db 01100000b db 06h db 00h db 07h db 00h db 09h db 00000001b db 0ah ...
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Application Note The Z180™ Interfaced with the SCC at MHZ (Continued) Table 14. Test Program – Z180/SCC DMA Transfer (Continued) ;source/dist addr table for Z180’s dma addrtab: ;interrupt vector table z180vect: tx_buff: rx_buff: temp: end 7-32 db 01h db 11100000b ...
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... This program example specifies a way to initialize the SCC and the Z180 DMA. For further design assistance, a completed board together with the Debug/Monitor program and the listed sample program are available. If interested, please contact your local Zilog sales office. Application Note 7 7-23 ...
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UM011001-0601 ...
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... Intel environment. INTRODUCTION Zilog’s customers need a way to evaluate its serial communications controllers with a central CPU. This App Note (Application Note) explains and illustrates how the datacom family interfaces and communicates with the 80186 on this evaluation board ...
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... Table 2. Counter/Timer Signal Locations J26 pin The 80186’s integrated interrupt controller is largely bypassed in favor of the traditional Zilogical interrupt daisy-chain structure. Install this jumper: J23-1 to J23-2 J22-1 to J22-2 J22-4 to J22-2 J29-1 to J29-2 J29-4 to J29-2 Install this Jumper: J24-1 to J24-3 ...
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... In particular, the UMCS register (address A0H within the 80186’s Peripheral Control Block) UM011001-0601 The Zilog Datacom Family with the 80186 CPU addresses of the datacom controllers are programmed in the 80186 for the /PCS6-/PCS0 outputs block of 128x7=896 bytes starting Kbyte boundary. The block can be in I/O space part of memory space that is not used for SRAM or EPROM ...
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... Application Note The Zilog Datacom Family with the 80186 CPU RAM Six 32-pin sockets are provided; they should be populated in pairs, starting with the lower-numbered sockets, to allow for 16-bit accesses provided at both pin 32 and pin that 28-pin 32K x 8 SRAMs can be installed in pins ...
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... This variability is provided in part because early versions of the 85230 ESCC had trouble passing an interrupt acknowledge down the daisy chain if it occurred in UM011001-0601 The Zilog Datacom Family with the 80186 CPU Table 6. Address Ranges for Reset Address Range for which ISCC, MMCS value ...
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... Application Note The Zilog Datacom Family with the 80186 CPU (E)SCC Socket U2 can be configured for either an ESCC or SCC, and for versions thereof that use either multiplexed or non- multiplexed address and data. Jumper blocks J20 and J21 select certain signals accordingly. For a part with ...
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... A/B selection is taken from A5 of the multiplexed address.) UM011001-0601 The Zilog Datacom Family with the 80186 CPU basic (E)SCC register map occurs twice in the even addresses from (PBA) through (PBA)+126: Channel B registers 0-15 ...
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... Application Note The Zilog Datacom Family with the 80186 CPU The fact that the ISCC’s internal logic sees activity on its /AS pin, which is inverted from the 80186' ALE signal, automatically conditions it Address/Data bus. (PBA)+128, 130, ..., (PBA)+190 (PBA)+192, 194, ..., (PBA)+222 (PBA)+224, 226, ...
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... IUSC. Bits 14-8 are more or less required to be all 0 by the IUSC’s internal logic. UM011001-0601 The Zilog Datacom Family with the 80186 CPU Registers Accessed 16-bit access to MUSC regs or USC channel B regs 8-bit access to MUSC regs or USC channel B regs 16-bit access to MUSC regs or USC channel A regs ...
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... Application Note The Zilog Datacom Family with the 80186 CPU IUSC (Continued) Starting Addr Ending Addr (PBA)+512 (PBA)+575 (PBA)+576 (PBA)+639 (PBA)+640 (PBA)+703 (PBA)+704 (PBA)+767 (PBA)+768 (PBA)+831 (PBA)+832 (PBA)+895 While the ESCC and ISCC can drive their Baud Rate Generators from their PCLK inputs, the IUSC cannot do this from its CLK input ...
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... Note: [3] Various conventions have been used to combine synchronous clock inputs and modem control inputs on Apple Macintosh connectors similar to J4, as described in a later section. UM011001-0601 The Zilog Datacom Family with the 80186 CPU Connect the connector(s) from the previous table to: J13 J14 ...
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... Application Note The Zilog Datacom Family with the 80186 CPU SERIAL INTERFACING (Continued) Table 10. Pin Assignments of Line Driver/Receiver Connectors J13-J14 J13-J14 Pin # DTE signal DCE signal 7 /DCD 8 /DCD 9 10 GND GND 11 /RxC 12 /RxC 13 /TxCO /TxCI 14 /TxCI /TxCO 15 /RI 16 /RI Note: [3] Various conventions have been used to combine synchronous clock inputs and modem control inputs on Apple Macintosh connectors similar to J4, as described in a later section ...
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... the (M)USC; in fact, it includes most of the code necessary to use any of the six serial controller channels for the Console. UM011001-0601 The Zilog Datacom Family with the 80186 CPU Notes on J4/Macintosh/AppleTalk/LocalTalk The J4 connector is similar to that offered on various Macintosh systems. The ESCC and ISCC are particularly ...
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... Application Note The Zilog Datacom Family with the 80186 CPU SERIAL INTERFACING (Continued) With jumpers installed to make DCD and CTS unbalanced, J4 can also be used for an additional RS-232 serial link. Connect a “Mac to Hayes modem” cable to J4, and optionally a null modem interconnect module to the other end. The cable internally grounds the RxD+ and TxD+ leads so that RxD– ...
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... J29-J1 thru - USC B RxREQ on DMA USC B RxREQ on DMA USC B TxREQ on DMA USC B TxREQ on DMA 1 UM011001-0601 The Zilog Datacom Family with the 80186 CPU actual connectors meant for use with cables, jumper wires, or wire-wrapped connections. Table 12. Two-Pin Option Jumpers Application Note Open ...
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... Application Note The Zilog Datacom Family with the 80186 CPU DMA/EPLD LOGIC 9-16 Figure 1. Control EPLD for 186 Board UM011001-0601 ...
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... UM011001-0601 The Zilog Datacom Family with the 80186 CPU Figure 2. SCC EPLD for 186 Board Application Note 8 9-17 ...
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... Application Note The Zilog Datacom Family with the 80186 CPU DMA/EPLD LOGIC (Continued) 9-18 Figure 3. DMA EPLD for 186 Board UM011001-0601 ...
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... UM011001-0601 The Zilog Datacom Family with the 80186 CPU Figure 4. NMI Field for 186 Board Application Note 8 9-19 ...
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... Application Note The Zilog Datacom Family with the 80186 CPU 9-20 Figure 5. Schematic of the Evaluation Board UM011001-0601 ...
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... S YNCHRONOUS INTRODUCTION Zilog’s Z8030 Z-SCC Serial Communications Controller is one of a family of components that are Z-BUS with the Z8000™ CPU. Combined with a Z8000 CPU (or other existing 8- or 16-bit CPUs with nonmultiplexed buses when using the Z8530 SCC), the Z-SCC forms an ...
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Application Note SCC in Binary Synchronous Communications SYNCHRONOUS MODES Three variations of character-oriented synchronous communications are supported by the Z-SCC: Mono-sync, Bisync, and External Sync (Figure 1). In Monosync mode, a single sync character is transmitted, which is then compared ...
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Address Reset Reset Switch NMI Non-maskable Switch Interrupt Segment Address Control Buffer Inputs Clock External Clock In/Out Clock Generator Figure 3. Block Diagram of Two Z8000 Development Modules UM011001-0601 Address/ Data Data Buffer Segment Z80A PIO's Address (2) Buffer Status ...
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Application Note SCC in Binary Synchronous Communications SYSTEM INTERFACE (Continued) 10-4 Figure 4. Z8002 with SCC UM011001-0601 ...
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When the Z8002 CPU uses the lower half of the Address/Data bus (AD0-AD7 the least significant byte) for byte read and write transactions during I/O operations, these transactions are performed between the CPU and I/O ports located at odd I/O ...
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Application Note SCC in Binary Synchronous Communications INITIALIZATION (Continued) The Z8002 CPU must be operated in System mode in order to execute privileged I/O instructions, so the Flag Control Word (FCW) should System/Normal (S//N), and the Vectored Interrupt Enable (VIE) ...
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TRANSMIT OPERATION To transmit a block of data, the main program calls up the transmit data routine. With this routine, each message block to be transmitted is stored in memory, beginning with location ‘TBUF’. The number of characters contained in ...
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Application Note SCC in Binary Synchronous Communications APPENDIX SOFTWARE ROUTINES plzasm 1.3 LOC OBJ CODE STMT SOURCE 1 $LISTON CONSTANT WR0A RR0A RBUF PSAREA COUNT 0000 GLOBAL MAIN PROCEDURE ENTRY 0000 7601 0002 4400 0004 7D1D 0006 2100 0008 5000 ...
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INITIALIZATION ROUTINE FOR Z-SCC 0034 GLOBAL ENTRY 0634 2100 0036 000F 0038 7602 003A 004E' 003C 2101 ALOOP: 003E FE21 0040 0029 0042 A920 0044 3A22 0046 0018 0048 8D04 004A EEF8 004C 9E08 004E 12 SCCTAB: 004F CO 0050 ...
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Application Note SCC in Binary Synchronous Communications RECEIVE ROUTINE RECEIVE A BLOCK OF MESSAGE THE LAST CHARACTER SHOULD BE EOT (%04) GLOBAL 006C ENTRY 006C C828 006C 3A86 0070 FE23 0072 6000 0074 00AB 0076 3A86 0078 FE23 007A 2101 ...
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TRANSMIT ROUTINE SEND A BLOCK OF DATA CHARACTERS THE BLOCK STARTS AT LOCATION TBUP GLOBAL OA6 ENTRY TRANSMIT 00A6 2102 LD 00AB 0028' 00AA C86C LDB 00AC 3AB6 OUTB 00AE FE2B 00B0 C800 LDB 00B2 3A86 OUTB 00B4 FE23 00B6 ...
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Application Note SCC in Binary Synchronous Communications RECEIVE INT. SERVICE ROUTINE GLOBAL 00F4 ENTRY 00F4 93F0 00F6 3A84 00F8 FE21 00FA A684 00FC EE02 00FE 5F00 0100 006C’ 0102 C808 RESET: 0104 3A86 0106 FE23 0108 C8D1 010A 3A86 010C ...
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SPECIAL CONDITION INTERRUPT SERVICE ROUTINE GLOBAL 011E ENTRY 011E 93F0 0120 3A84 0122 FE23 0124 C830 0126 3A8B6 0128 FE21 012A C808 012C 3A86 012E FE23 0130 C0D1 0132 3A86 0134 FE27 0136 C838 0138 3A86 013A FE21 013C 97F0 ...
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UM011001-0601 ...
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... Serial Communication Controller operating in the SDLC mode simplifies working in this complex area. INTRODUCTION Zilog’s SCC (Serial Communication Controller popular USART (Universal Synchronous/Asynchronous Receiver/Transmitter) device, used for a wide range of applications. For instance, Macintosh systems use the SCC as a standard communication controller device ...
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Application Note Serial Communication Controller (SCC SDLC TRANSMIT Figure 1 shows the time chart for the transmitting SDLC packet under interrupt control. When transmit is engaged, data is shifted out of the transmitter on the falling edge of the transmit ...
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Notes on Figure 1: 1. The SCC has two possible idle states, Mark idle (contiguous logic 1) or Flag idle (repeating flag pattern 7EH). In this figure, the SCC has to be switched to flag idle in order to send ...
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Application Note Serial Communication Controller (SCC SDLC RECEIVE There are several different ways to receive a SDLC packet on the SCC; by polling, by Interrupts and by DMA. The SCC has the following four Receive Interrupt Modes: Disabled. This should ...
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Figure 2. Typical SDLC Receive Sequence with Receive Interrupts on all Received UM011001-0601 Serial Communication Controller (SCC Characters or Special Condition Application Note ™ ): SDLC Mode of Operation 1 11-5 ...
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Application Note Serial Communication Controller (SCC RECEIVE INTERRUPTS ON FIRST CHARACTER OR SPECIAL CONDITIONS The sequence of events in this mode is similar to that in “Receive Interrupts on all received characters and Special Conditions”, except that it generates Receive ...
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Notes on Figure 3: 1. The receiver is usually in hunt mode when waiting for a frame. When the opening flag is received, an External/Status Interrupt is generated, indicating the change from hunt mode to sync mode. 2. The /SYNC ...
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Application Note Serial Communication Controller (SCC RECEIVE INTERRUPTS ON SPECIAL CONDITIONS ONLY The sequence of event in this mode is similar to that for “Receive Interrupts on first received character or Special Condition,” except it will not generate Receive Character ...
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Figure 4. Receiving “Back to Back” frame with Receive Interrupts on Special Condition UM011001-0601 Serial Communication Controller (SCC Only Mode (DMA Controlled) Application Note ™ ): SDLC Mode of Operation 1 11-9 ...
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Application Note Serial Communication Controller (SCC THE SDLC LOOP MODE The SDLC Loop mode is one of the protocols used in the ring configuration network topology. The typical network configuration is shown in Figure 5. As shown, there is one ...
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UM011001-0601 Serial Communication Controller (SCC Figure 6. SDLC Loop Mode Application Note ™ ): SDLC Mode of Operation 1 11-11 ...
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Application Note Serial Communication Controller (SCC THE SDLC LOOP MODE (Continued) Notes on Figure 6: 1. The master SCC sends EOP by switching from flag on idle to mark on idle 2. At initialization, all Slave stations were set up ...