Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 46

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
It is sometimes desirable to prevent sync characters from
entering the receive data FIFO. This function is available
in the ISCC by setting the Sync Character Load inhibit bit
(D1) in WR3 to “1”. While this bit is set to “1”, the character
about to be loaded into the receive data FIFO is compared
with the contents of WR6. If all eight bits match the char-
acter, it is not loaded into the receive data FIFO. Because
the comparison is across eight bits, this function works cor-
rectly only when the number of bits per character is the
same as the sync character length. Thus it cannot be used
with 12- or 16-bit sync characters. Both leading sync char-
acters and sync characters embedded in the data may be
properly removed in the case of a 8-bit sync character.
Care must be exercised in using this feature because sync
characters not transferred to the receive data FIFO will au-
tomatically be excluded from CRC calculation. This works
properly only in the 8-bit case.
The receiver in the ISCC searches for character synchro-
nization only while it is in Hunt mode. In this mode the re-
ceiver is idle having been first enabled, and may be placed
in Hunt mode by command from the processor. This is ac-
complished by issuing the Enter Hunt Mode command in
WR3. This bit (D4) is a command; writing a “0” to it has no
effect. The Hunt status of the receiver is reported by the
Sync/Hunt is one of the possible sources of external/status
interrupts, with both transitions causing an interrupt. This
is true even if the Sync/Hunt bit is set as a result of the pro-
cessor issuing the Enter Hunt Mode command.
4-12
/SYNC
/RTxC
PCLK
Figure 4-7. /SYNC as an Output
The number of bits per character is controlled by bits D7
and D6 of WR3. Five, six, seven, or eight bits per character
may be selected via these two bits. The data is right-justi-
fied in the receive data buffer. The ISCC merely takes a
snapshot of the receive data stream at the appropriate
times so the “unused” bits in the receive buffer are only the
bits following the character in the data stream.
An additional bit, carrying parity information, may be se-
lected by setting bit D0 of WR4 to “1”. If this bit is set to “1”,
the received character is checked for even parity, if set to
“0”, the received character is checked for odd parity. The
additional bit per character is not visible when there are
eight data bits per character. The Parity Error bit in the re-
ceive error FIFO may be programmed to cause a Special
Receive Condition interrupt by setting bit D2 of WR1 to “1”.
This error bit is latched and so will remain active, once set,
until an Error Reset command has been issued. If inter-
rupts are not used to transfer data the Parity Error, CRC
Error, and Overrun Error bits in RR1 should be checked
before the data is removed from the receive data FIFO.
The character length may be changed at any time before
the new number of bits has been assembled by the
receiver, but, care should be exercised as unexpected
results may occur. A representative example, switching
from five bits to eight bits and back to five bits is shown in
Figure 4-8.
State changes in one
/RTxC clock cycle
UM011001-0601