Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 56

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Data Communication Modes
4.4 BIT-ORIENTED SYNCHRONOUS MODE (Continued)
As an example of how the codes are interpreted, consider
the case of eight bits per character and a residue code of
101. The number of valid bits for the previous, second
previous, and third previous bytes are 0, 7, and 8
respectively. This indicates that the information field (I-
field) boundary falls on the second previous byte as shown
in Figure 4-14.
A frame is terminated by the detection of a closing flag.
Upon detection of the flag the following actions take place:
the contents of the Receive Shift Register are transferred
to the receive data FIFO, the Residue Code is latched, the
CRC Error bit is latched and the End of Frame upon reach-
ing the top of the FIFO can cause a special receive condi-
tion. The processor can then read RR1 to determine the
result of the CRC calculation as well as the Residue Code.
Only the CRC-CCITT polynomial may be used for CRC
calculation in SDLC mode, although the generator and
checker may be preset to all “1s” or all “0s”. The CRC-
CCITT polynomial is selected by setting bit D2 of WR5 to
“0”, bit D7 of WR10 controls the preset value. If this bit is
set to “1”, the generator and checker are preset to “1s”, if
this bit is reset, the generator and checker are present to
all “0s”.
The receiver expects the CRC to be inverted before trans-
mission and so checks the CRC result against the value
“0001110100001111”. The ISCC presets the CRC check-
er whenever the receiver is in Hunt mode or whenever a
flag is received so a CRC reset command is not strictly
necessary. However, the CRC checker may be preset by
issuing the Reset CRC Checker command in WR0.
The CRC checker is automatically enabled for all data be-
tween the opening and closing flags by the SCC cell in
SDLC mode, and the Rx CRC Enable bit (D3) in WR3 is
ignored. The result of the CRC calculation for the entire
frame is valid in RR1 only when accompanied by the End
of Frame bit being set in RR1. At all other times the CRC
Error bit in RR1 should be ignored by the processor.
Care must be exercised so that the processor does not at-
tempt to use the CRC bytes that are transferred as data
because not all of the bits are transferred properly. The last
4-22
Figure 4-14. Residue Code 101 Interpretation
Third Previous
Byte
Second Previous
7 Bits
Byte
I-Field
CRC Field
Previous Byte
two bits of CRC are never transferred to the receive data
FIFO and are not recoverable.
Note the following about ISCC CRC operation:
The normal CRC checking mechanism involves checking
over data and CRC characters. If the division remainder is
0, there is no CRC error.
SDLC is different. The CRC generator, when receiving a
correct frame, will have a fixed, non-zero remainder. The
actual remainder in the receive CRC calculation must be
checked against this fixed value to determine if a CRC
error exists.
A frame is terminated by a closing flag. When the ISCC
recognizes this flag:
The contents of the Receive Shift register are transferred
to the receive data FIFO.
The Residue Code is latched, and the CRC Error bit is
latched in the status FIFO and the End of Frame bit is set
in the receive status FIFO.
The End of Frame bit, upon reaching the top of the FIFO,
will cause a special receive condition. The processor may
then read RR1 to determine the result of the CRC calcula-
tion as well as the Residue Code. If either the Rx Interrupt
or Special Condition Only or the Rx Interrupt on First Char-
acter or Special Condition modes are selected, the FIFO
will be locked, and the processor must issue an Error Re-
set command in WR0 to unlock the receive FIFO.
In addition to searching the data stream for flags, the re-
ceiver in the ISCC also watches for seven consecutive
“1s”, which is the abort condition. The presence of seven
consecutive “1s” is reported in the Break/Abort bit in RR0.
This is one of the possible external/status interrupts, so
transitions of this status may be programmed to cause in-
terrupts. Upon receipt of an abort the receiver is forced into
Hunt mode where it looks for flags. The Hunt status is also
a possible external/status condition whose transition may
be programmed to cause an interrupt. The transitions of
these two bits occur very close together but either one or
two external/status interrupts may result. The abort condi-
tion is terminated when a “0” is received, either by itself or
as the leading “0” of a flag. The receiver does not leave
Hunt mode until a flag has been received so two discrete
external/status conditions will occur at the end of an abort.
An abort received in the middle of a frame terminates the
frame reception, but not in an orderly manner, because the
character being assembled is lost.
Up to two modem control signals associated with the re-
ceiver are available in SDLC mode:
UM011001-0601