Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 21

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
3.1 INTRODUCTION
The most important feature of the ISCC other than SCC
cell is the integrated, four channel DMA controller. As in the
original SCC, the serial channels of the ISCC are support-
3.2 DMA
The ISCC™ contains four independent DMA Channels,
one for each receiver and transmitter. The DMA channels
operate in fly-by mode; a 32-bit transfer address is gener-
ated along with the bus acquisition signals for executing
the DMA transfer. Each DMA consists of a 32-bit address
counter, a 16-bit (transfer) counter, and the required se-
quencing and control circuitry.
The DMA is set up by initializing the address resisters with
the starting address of the DMA transfer and the count reg-
isters for the length of the block. Following this, the option
to increment or decrement the address after a transfer is
selected. Other DMA selections that must be programmed
include the DMA priority, if separate bus requests are to be
made for each DMA channel, the programming of the inter-
rupt vector and the option to include interrupt status in the
vector. Note that a no vector interrupt option is also possi-
ble. Following this, the Interrupt On Abort is programmed
as desired, the individual channel interrupt enables are
programmed, the Master Interrupt Enable is set (if inter-
rupts are used), and lastly the appropriate DMA channels
are enabled.
3.2.1 Receiver DMA Operation
Assuming the receiver has been appropriately set up, the
DMA request will be made when the receive FIFO contains
a byte and will continue to hold the bus and transfer bytes
until the FIFO is empty. Once started, the DMA for the
channel continues until the FIFO is empty even though a
request from a higher priority DMA channel arises. Upon
completion of the current DMA channel service, the next
highest priority DMA channel commences its operation.
The ISCC continues to hold the bus until all pending DMA
requests have been served. Note that if the Bus Request
U
C
ISCC™ DMA
S
ed by ancillary circuitry for generating clocks and perform-
ing data encoding and decoding. This chapter presents a
description of these functional blocks.
Per Channel option has been selected, then the bus will be
released and subsequently re-requested for each channel.
At the completion of the block transfer (terminal count
reached), an interrupt will be generated, if enabled. If se-
lected, the interrupt vector will indicate the interrupt source
according to Table 3-1.
An Interrupt Pending only modifies the interrupt vector if
the corresponding Interrupt Enable bit is set. Note that soft-
ware may have to test status bits to determine if the chan-
nel interrupt is due to terminal count or an abort.
When the receive DMA enable bit is set, a DMA request is
made if the receive FIFO contains a character at the time,
or no request will be made until a character enters the re-
ceive FIFO. Note that DMA requests will follow the state of
the receive FIFO even though the receiver is disabled.
Thus, if the receiver is disabled and the DMA is still en-
abled, the DMA will transfer the previously received data
correctly. In this mode the DMA requests directly follow the
state of the receive FIFO. This operation is essentially
equivalent to the DMA requests following the state of the
SER
UPPORT
HAPTER
IV3
0
0
0
0
1
1
1
1
Table 3-1. DMA Interrupt Vector Modification
’
S
M
ANUAL
IV2
0
0
1
1
0
0
1
1
C
IRCUITRY
AND
3
IV1
0
1
0
1
0
1
0
1
A
NCILLARY
Interrupt Source
No Interrupt Pending
Not Possible
Not Possible
Not Possible
Rx A Interrupt Pending
Rx B Interrupt Pending
Tx A Interrupt Pending
Tx B Interrupt Pending
3-1
3