Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 17

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
2.4.3 SCC Cell Register Reset
Table 2-5 lists the contents of the SCC cell registers after
a hardware reset and after a channel reset.
Table 2-4. SCC Cell Register Address Map Using
A1/A//B
A1/A//B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Pointer (Non-multiplexed Bus Mode)
Using Point High Command
D2 D1 D0
D2 D1 D0
Address
Address
Using Null Command
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Register
Register
WR10B
WR11B
WR12B
WR13B
WR14B
WR15B
WR10A
WR11A
WR12A
WR13A
WR14A
WR15A
WR0B
WR1B
WR3B
WR4B
WR5B
WR6B
WR7B
WR0A
WR1A
WR3A
WR4A
WR5A
WR6A
WR7A
WR8B
WR8A
WR9A
Write
Write
WR2
WR2
WR9
Register
Register
(RR15B)
(RR10B)
(RR13A)
(RR15A)
(RR10A)
(RR0B)
(RR1B)
(RR2B)
(RR3B)
(RR0A)
(RR1A)
(RR2A)
(RR3A)
RR13B
RR10B
RR12B
RR13B
RR15B
RR10A
RR12A
RR13A
RR15A
RR0B
RR1B
RR2B
RR3B
RR0A
RR1A
RR2A
RR3A
RR8B
RR8A
Read
Read
2.4.4 DMA Cell Registers
The DMA cell contains seventeen registers counting the
Bus Configuration Register. All of these registers are
read/write except the Bus Configuration Register (write
only), the Channel Command Address Register (write
only), the DMA Status Register (read only), the Interrupt
Command Register (write only), and the Interrupt Status
Register (read only).
The reset content of all of the DMA registers identified in
the address map is all zeros.
2.4.5 DMA Register Access, Multiplexed Bus
The registers in the ISCC in the multiplexed bus mode are
addressed via the address on AD7-AD0 which is latched
by the rising edge of /AS.
There are two address decoding modes: shift left and shift
right. In shift left mode, the register address is decoded
from AD5-AD1. This mode is set by a hardware reset. In
shift right mode, the register address is decoded from
AD4-AD0. The shift right/shift left selection for the DMA is
located in the Bus Configuration Register, bit D0. When
set, this bit programs the Shift Right mode for the DMA and
when reset, this bit programs the Shift Left mode.
The address map for the DMA registers is shown in Table
2-6. This Table is also applicable to the non-multiplexed
bus mode.
Register
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
WR9
WR10
WR11
WR12
WR13
WR14
WR15
RR0
RR1
RR3
RR10
Table 2-5. SCC Cell Reset Value
Hardware Reset
00000000
00000000
00001000
11111000
00000110
00000000
00000000
00x00x00
0xx0000x
110000xx
xx100000
01xxx100
xxxxxxx0
xxxxx1xx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
Z16C35 ISCC™ User’s Manual
Interfacing the ISCC™
Channel Reset
00000000
11111000
00000110
00000000
00000000
00x00x00
0xx00000
0xx0000x
xx1000xx
01xxx100
xxxxxxxx
xxxxxxx0
xxxxx1xx
xxxxxxxx
xxxxxxxx
xx0xxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
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