Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 77

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Bits 4 and 3 are the Transmit Clock select bits 1 and 0
These bits determine the source of the transmit clock as
shown in Table 5-10. They do not interfere with any of the
modes of operation of the ISCC, but simply control a mul-
tiplexer just before the internal transmit clock input. The
DPLL output that may be used to feed the transmitter in
FM modes lags by 90 degrees the output of the DPLL used
by the receiver. This makes the received and transmitted
bit cells occur simultaneously, neglecting delays. A hard-
ware reset selects the /TRxC pin as the source of the
transmit clocks.
Bit 2 is the TRxC Pin O//I control bit
This bit determines the direction of the /TRxC pin. If this bit
is set to “1,” the TRxC pin is an output and carries the sig-
nal selected by D1 and D0 of this register. However, if ei-
ther the receive or the transmit clock is programmed to
come from the /TRxC pin, /TRxC will be an input, regard-
less of the state of this bit. The /TRxC pin is also an input
if this bit is set to “0” A hardware reset forces this bit to “0.”
Bits 1 and 0 are the /TRxC Output Source select bits 1
and 0
These bits determine the signal to be echoed out of the
ISCC via the /TRxC pin as given in Table 5-11. No signal is
produced if /TRxC has been programmed as the source of
either the receive or the transmit clock. If TRxC O//I (bit 2) is
set to “0,” these bits are ignored.
If the XTAL oscillator output is programmed to be echoed,
and the XTAL oscillator has not been enabled, the /TRxC
pin goes High. The DPLL signal that is echoed is the DPLL
signal used by the receiver. Hardware reset selects the
XTAL oscillator as the output source.
Bit 6
Bit 4
0
0
1
1
0
0
1
1
Table 5-10. Transmit Clock Source
Table 5-9. Receive Clock Source
Bit 5
Bit 3
0
1
0
1
0
1
0
1
Receive Clock
RTxC Pin
TRxC Pin
BR Output
DPLL Output
Transmit Clock
RTxC Pin
TRxC Pin
BR Output
DPLL Output
P R E L I M I N A R Y
5.4.13 Write Register 12 (Lower Byte of Baud
Rate Generator Time Constant)
WR12 contains the lower byte of the time constant for the
baud rate generator. The time constant can be changed at
any time, but the new value does not take effect until the
next time the time constant is loaded into the down
counter. No attempt is made to synchronize the loading of
the time constant into WR12 and WR13 with the clock driv-
ing the down counter. For this reason, it is advisable to dis-
able the baud rate generator while the new time constant
is loaded into WR12 and WR13. Ordinarily, this is done
anyway to prevent a load of the down counter between the
writing of the upper and lower bytes of the time constant.
The formula for determining the appropriate time constant
for a given baud is shown below with the desired rate in bits
per second and the BR clock period in seconds. This formu-
la is derived because the counter decrements from N down
to “0”-plus-one-cycle for reloading the time constant and is
then fed to a toggle flip-flop to make the output a square
wave. Bit positions for WR12 are shown in Figure 5-14.
Time constant = [1/2 * desired rate * BR clock period] - 2
Write Register 12
D7
Table 5-11. Transmit External Control Selection
Bit 1
D6
0
0
1
1
D5 D4 D3 D2 D1 D0
Figure 5-14. Write Register 12
Bit 0
0
1
0
1
TRxC Pin Output
XTAL Oscillator Output
Transmit Clock
BR Output
DPLL Output (receive)
Z16C35ISCC™ User’s Manual
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
Register Descriptions
Lower
Byte of
Time
Constant
5-17
5