Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 47

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Either of two CRC polynomials may be used in synchro-
nous modes, selected by bit D2 in WR5. If this bit is set to
“1”, the CRC-16 polynomial is used, if this bit is set to “0”,
the CRC-CCITT polynomial is used. This bit controls the
polynomial selection for both the receiver and transmitter.
The initial state of the generator and checker is controlled
by bit D7 of WR10. When this bit is set to “1”, both the gen-
erator and checker will have an initial value of all ones, if
this bit is set to “0”, the initial values will be all “0s”. The
ISCC presets the checker whenever the receiver is in Hunt
mode so a CRC reset command is not strictly necessary.
However, there is a Reset CRC Checker command in
WR0. This command is encoded in bits D7 and D6 of
WR0. If CRC is to be used the CRC checker must be en-
abled by setting bit D0 of WR3 to “1”.
If sync characters are being stripped from the data stream,
this may be done at any time before the first non-sync
character is received. If the sync strip feature is not being
used, CRC must not be enabled until after the first data
character has been transferred to the receive data FIFO.
As previously mentioned, 8-bit sync characters stripped
from the data stream are automatically excluded from
CRC calculation.
Some synchronous protocols require that certain charac-
ters be excluded from CRC calculation. This is possible in
the ISCC because CRC calculation may be enabled and
Change from Five to Eight
Change from Eight to Five
Figure 4-8. Changing Character Length
Time
13
21
29
34
39
8
disabled on the fly. To give the processor sufficient time to
decide whether or not a particular character should be in-
cluded in the CRC calculation, the ISCC contains an 8-bit
time delay between the receive shift register and the CRC
checker. The logic also guarantees that the calculation will
only start or stop on a character boundary by delaying the
enable or disable until the next character is loaded into the
receive data FIFO.
To understand how this works refer to Figure 4-9 and the
following explanation. Consider a case where the ISCC re-
ceives a sequence of eight bytes, called A, B, C, D, E, F,
G and H with A received first. Now suppose that A is the
sync character, that CRC is to be calculated on B, C, E,
and F, and that F is the last byte of this message. A pro-
cess is used to control the ISCC as described below.
The Receive Character-Operational Stages:
1. Before A is received the receiver is in Hunt mode and
2. After 8-bit times, B is loaded into the receive data
12
20
28
33
38
7
Receive Data Buffer
the CRC is disabled. When A is in the receive shift
register it is compared with the contents of WR7. Since
A is the sync character, the bit patterns match and
receive leaves Hunt mode, but character A is not
transferred to the receive data FIFO.
FIFO. The CRC remains disabled even though
somewhere during the next eight bit times the
11 10 9
19 18 17 16 15 14
27 26 25 24 23 22
32 31 30 29 28 27
37 36 35 34 33 32
6
5
4
3
8
2
7
1
6
Z16C35ISCC™ User’s Manual
Data Communication Modes
5 Bits
8 Bits
8 Bits
5 Bits
5 Bits
4-13
4