Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 64

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Register Descriptions
5.4 WRITE REGISTERS (Continued)
The following bit description for WR0 is identical for both
versions except where specified.
Bits D7 and D6 are the CRC Reset Codes 1 and 0.
Bit combination 00 is a Null Command
This command has no effect on the ISCC SCC cell and is
used when a write to WR0 is necessary for some reason
other than a CRC Reset command.
Bit combination 01 is the Reset Receive CRC Checker
Command
This command is used to initialize the receive CRC circuit-
ry. It is necessary in synchronous modes (except SDLC) if
the Enter Hunt Mode command in Write Register 3 is not
issued between received messages. Any action that dis-
ables the receiver initializes the CRC circuitry. Resetting
the Receive CRC Checker command is accomplished au-
tomatically in SDLC mode.
Bit combination 10 is the Reset Transmit CRC Gener-
ator Command
This command initializes the CRC generator. It is usually
issued in the initialization routine and after the CRC has
been transmitted. A Channel Reset will not initialize the
generator and this command should not be issued until af-
ter the transmitter has been enabled in the initialization
routine.
Bit combination 11 is the Reset Transmit Under-
run/EOM Latch Command
This command controls the transmission of CRC at the
end of transmission (EOM). If this latch has been reset,
and a transmit underrun occurs, the SCC cell automatical-
ly appends CRC to the message. In SDLC mode with
Abort on Underrun selected, the SCC cell sends an abort,
and Flag on underrun if the TX Underrun/EOM latch has
been reset.
At the start of the CRC transmission, the Tx Under-
run/EOM latch is set. The Reset command can be issued
at any time during a message. If the transmitter is disabled,
this command will not reset the latch. However, if no Exter-
nal Status interrupt is pending, or if a Reset External Sta-
tus interrupt command accompanies this command while
the transmitter is disabled, an External/Status interrupt is
generated with the Tx Underrun/EOM bit reset in RR0.
Bits D5-D3 are the Command Codes for the SCC Cell.
Bit combination 000 is a Null Command.
The Null command has no effect on the SCC.
5-4
P R E L I M I N A R Y
Bit combination 001 is the Point High Command
This command effectively adds eight to the Register Point-
er (D2-D0) by allowing WR8 through WR15 to be access-
ed. The Point High command and the Register Pointer bits
are written simultaneously. This command is used when
the ISCC is configured to be in the non-multiplexed bus
mode. Note that WR0 changes form depending upon the
bus mode selection.
Bit combination 010 is the Reset External/Status
Interrupts Command
After an External/Status interrupt (a change on a modem
line or a break condition, for example), the status bits in
RR0 are latched. This command re-enables the bits and
allows interrupts to occur again as a result of a status
change. Latching the status bits captures short pulses until
the CPU has time to read the change.
The SCC cell contains simple queueing logic associated
with most of the external status bits in RR0. If another Ex-
ternal/Status condition changes while a previous condition
is still pending (Reset External/Status Interrupts has not
yet been issued) and this condition persists until after the
command is issued, this second change causes another
External/Status interrupt. However, if this second status
change does not persist (there are two transitions), anoth-
er interrupt is not generated. Exceptions to this rule are de-
tailed in the RR0 description.
Bit combination 011 is the Send Abort Command
This command is used in SDLC mode to transmit a se-
quence of eight to thirteen “1s.” This command always
empties the transmit buffer and sets Tx Underrun/EOM bit
in Read Register 0.
Bit combination 100 is the Enable Interrupt On Next Rx
Character Command
If the interrupt on First Received Character mode is select-
ed, this command is used to reactivate that mode after
each message is received. The next character to enter the
receive FIFO causes a Receive interrupt. Alternatively, the
first previously stored character in the FIFO will cause a
Receive interrupt.
Bit combination 101 is the Reset Tx Interrupt Pending
Command
This command is used in cases where there are no more
characters to be sent; e.g., at the end of a message. This
command prevents further transmit interrupts until after
the next character has been loaded into the transmit buffer
or until CRC has been completely sent. This command is
necessary to prevent the transmitter from requesting an in-
terrupt when the transmit buffer becomes empty (with
Transmit Interrupt Enabled).
UM011001-0601