Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 8

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35 ISCC™ User’s Manual
General Description
1.3 PIN DESCRIPTION
The following section describes the Z16C35 pin functions.
Figures 1-2 and 1-3 detail the respective pin functions and
pin assignments. All references to DMA are internal.
/CTSA, /CTSB. Clear To Send (inputs, active Low). These
pins function as transmitter enables if they are pro-
grammed for Auto Enables (WR3, D5). If these pins are
programmed as Auto Enables, a Low on the inputs en-
ables the respective transmitters. If not programmed as
Auto Enables, they may be used as general-purpose in-
puts. Both inputs are Schmitt-trigger buffered to accommo-
date slow rise-time inputs. The SCC cell detects transi-
tions on these inputs and can interrupt the CPU on both
low to high and high to low transitions.
/DCDA, /DCDB. Data Carrier Detect (inputs, active Low).
These pins function as receiver enables if they are pro-
grammed for Auto Enables (WR3 D5), otherwise they are
used as general-purpose input pins. Both pins are Schmitt-
trigger buffered to accommodate slow rise time signals.
The SCC cell detects transitions on these inputs and can
interrupt the CPU on both low to high and high to low tran-
sitions.
/DTR//REQA, /DTR//REQB. Data Terminal Ready/Re-
quest (outputs, active Low). These pins are programmable
(WR14, D2) to serve as either general-purpose outputs or
as DMA request lines. When programmed for the DTR
function These outputs follow the state programmed into
the DTR bit of Write Register 5 (WR5, D7). When pro-
grammed for the Ready mode, these pins serve as DMA
requests for the transmitter. Note that this DMA request is
not associated with the on-chip DMA and is intended for
use in requesting DMA service from an external DMA.
IEI. Interrupt Enable In (input, active High). IEI is used with
IEO to form an interrupt daisy chain when there is more
than one interrupt driven device. A high IEI indicates that
no other higher priority device has an interrupt under ser-
vice or is requesting an interrupt.
IEO. Interrupt Enable Out (output, active High). IEO is High
only if IEI is High and the CPU is not servicing the ISCC
(SCC or DMA) interrupt or the ISCC is not requesting an
interrupt (Interrupt Acknowledge cycle only). IEO is con-
nected to the next lower priority device’s IEI input and thus
inhibits interrupts from lower priority devices.
/INT. Interrupt (output, active Low). This signal is activated
when the SCC or DMA requests an interrupt. Note that
/INT is pulled high and is not an open-drain output.
/INTACK. Interrupt Acknowledge (input, active Low). This
is a strobe which indicates that an interrupt acknowledge
cycle is in progress. During this cycle, the SCC and DMA
interrupt daisy chain is resolved. The device is capable of
returning an interrupt vector that may be encoded with the
1-6
type of interrupt pending during this acknowledge cycle
when /RD or /DS become high. /INTACK may be pro-
grammed to accept a status acknowledge, a single pulse
acknowledge, or a double pulse acknowledge. This is pro-
grammed in the Bus Configuration Register (BCR). The
double pulse acknowledge is compatible with 8X86 family
microprocessors.
PCLK. Clock (input). This is the master SCC cell and DMA
cell clock used to synchronize internal signals. PCLK is a
TTL level signal. PCLK is not required to have any phase
relationship with the master system clock.
RxDA, RxDB. Receive Data (inputs, active High). These
input signals receive serial data at standard TTL levels.
/RTxCA, /RTxCB. Receive/Transmit Clocks (inputs, active
Low). These pins can be programmed to several modes of
operation. In each channel, /RTxC may supply the receive
clock, the transmit clock, the clock for the baud rate gener-
ator, or the clock for the Digital Phase-Locked Loop. These
pins can also be programmed for use with the respective
/SYNC pins as a crystal oscillator. The receive clock may
be 1, 16, 32, or 64 times the data rate in asynchronous
modes.
/RTSA, /RTSB. Request To Send (outputs, active Low).
When the Request To Send (RTS) bit in Write Register 5
is set, the /RTS signal goes Low. When the RTS bit is reset
in the Asynchronous mode and Auto Enable is on, the sig-
nal goes High after the transmitter is empty. In Synchro-
nous mode or in Asynchronous mode with Auto Enable off,
the /RTS pin strictly follows the state of the RTS bit. Both
pins can be used as general-purpose outputs.
/SYNCA, /SYNCB. Synchronization (inputs or outputs, ac-
tive Low). These pins can act either as inputs, outputs, or
part of the crystal oscillator circuit. In the Asynchronous
Receive mode (crystal oscillator option not selected),
these pins are inputs similar to /CTS and /DCD. In this
mode, transitions on these lines affect the state of the
Sync/Hunt status bits in Read Register 0 but have no other
function.
In External Synchronization mode with the crystal oscilla-
tor not selected, these lines also act as inputs. In this
mode, /SYNC must be driven Low two receive clock cycles
after the last bit in the synchronous character is received.
Character assembly begins on the rising edge of the re-
ceive clock immediately preceding the activation of
/SYNC.
In the Internal Synchronization mode (Monosync and Bi-
sync) with the crystal oscillator not selected, these pins act
as outputs and are active only during the part of the receive
clock cycle in which sync condition is not latched. These
outputs are active each time a sync pattern is recognized
UM011001-0601