Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 105

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Worst Case
6.
1.
2.
4.
8.
3.
7.
Worst Case
5.
Z8500A
Parameter
TsA(RD)
TdA(DR)
TdRDf(DR)
TwRD1
TsA(WR)
TsDW(WR)
TwWR1
Z8500A
Equation
TsA(WR)
TsA(RD)
TdA(DR)
TsCE1(WR)
TsCE1(RD)
TwRD1
TwWR1
TdRDf(DR)
TsDW(WR)
TcC
TwCh
TfC
TdCr(A)
TdCr(RDf)
TdCR(IORQf)
TdCr(WRf)
TsD(Cf)
Z80B
Equation
TcC-TdCr(A)
3TcC+TwCh-TdCr(A)-TsD(Cf)
2TcC+TwCh+TsD(Cf)
2TcC+TwCh+TfC-TdCr(RDf)
TcC-TdCr(A)
2 TcC+Twch+TfC-TdCr(WRf)
3TcC+TwCh-TdCr(A)-TdA(DR)
2TcC+TwCh-TdCr(RDf)-TdRD(DR)
Z80H CPU to Z8500 Peripherals
Address to /WR Low Setup
Address to /RD Low Setup
Address to Read Data Valid
/CE Low to /WR Low Setup
/CE Low to /RD Low Setup
/RD Low Width
/WR Low Width
/RD Low to Read Data Valid
Write Data to /WR Low Setup
Clock Cycle Period
Clock Cycle High Width
Clock Cycle Fall Time
Clock High to Address Valid
Clock High to /RD Low
Clock High to /IORQ Low
Clock High to /WR Low
Data to Clock Low Setup
Table 6. Z8500A Timing Parameters I/O Cycles
Table 7. Z80B Timing Parameters I/O Cycles
Table 8. Parameter Equations
Table 9. Parameter Equations
Interfacing Z80
®
CPUs to the Z8500 Peripheral Family
Value
>75 min
430 min
345 min
325 min
75 min
> 0 min
352 min
Value
50 min
75 min
Min
Min
165
65
80
80
250
250
0
40
Max
420
ns
ns
180
Max
20
90
70
65
60
Application Note
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
6-9
6