Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 5

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
1.2 FEATURES
Low Power CMOS Technology
Two General-Purpose SCC Channels, Four DMA
Channels; and Universal Bus Interface Unit
Software Compatible to the Zilog CMOS SCC
Four DMA Channels; Two Transmit and Two Receive
Channels to and from the SCC
Four Gigabyte Address Range per DMA Channel
Flyby DMA Transfer Mode
Programmable DMA Channel Priorities
Independent DMA Register Set
A Universal Bus Interface Unit Providing Simple
Interface to Most CPUs Multiplexed or Non-Multiplexed
Bus; Compatible with 680X0 and 8X86 CPUs
32-Bit Addresses Multiplexed to 16-pin Address/Data
Lines
8-Bit Data Supporting High/Low Byte Swapping
10 MHz Timing
12.5 and 16 MHz Timing Planned
68-Pin PLCC
Supports all Zilog CMOS SCC Features:
Two Independent, 0 to 4.0 Mbit/Second, Full-Duplex
Channels, Each with a Separate Crystal Oscillator,
Baud Rate Generator, and Digital Phase-Locked Loop
Circuit for Clock Recovery.
Multi-Protocol Operation under Program Control;
Programmable for NRZ, NRZI, or FM Data Encoding.
Asynchronous Mode with Five to Eight Bits and One,
One and One-Half, or Two Stop Bits per Character;
Programmable Clock Factor; Break Detection and
Generation; Parity, Overrun, and Framing Error
Detection.
Synchronous Mode with Internal or External Character
Synchronization on One or Two Synchronous
Characters and CRC Generation and Checking with
CRC-16 or CRC-CCITT preset to either 1’s or 0’s.
SDLC/HDLC Mode with Comprehensive Frame-Level
Control, Automatic Zero Insertion and Deletion, I-Field
Residue Handling, Abort Generation and Detection,
CRC Generation and Checking, and SDLC Loop Mode
Operation.
Local Loopback and Auto Echo modes
Supports T1 Digital Trunk
Enhanced SDLC 10x19 Status FIFO for DMA Support
Full CMOS SCC Register Set
Z16C35 ISCC™ User’s Manual
General Description
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