Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 58

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Data Communication Modes
4.4 BIT-ORIENTED SYNCHRONOUS MODE (Continued)
EOP so that it can go on loop. While waiting for the EOP,
the ISCC ties TxD to RxD with only the internal gate delays
in the signal path. When the first EOP is recognized by the
ISCC, the Break/Abort/EOP bit is set in RR0, generating
an External/Status interrupt (if so enabled). At the same
time, the On-Loop bit in RR10 is set to indicate that the
ISCC is indeed on-loop, and a one-bit time delay is insert-
ed in the TxD to the RxD path.
The ISCC is now on-loop but cannot transmit a message
until a flag and the next EOP are received. The require-
ment that a flag be received ensures that the ISCC cannot
erroneously send messages until the controller ends the
current polling sequence and starts another one.
If the CPU in the secondary station with ISCC needs to
transmit a message, the Go-Active-On-Poll bit in WR10
must be set. If this bit is set when the EOP is detected, the
ISCC changes the EOP to a flag and starts sending anoth-
er flag. The EOP is reported in the Break/Abort/EOP bit in
RR0 and the CPU should write its data bytes to the ISCC,
just as in normal SDLC frame transmission. When the
frame is complete and CRC has been sent, the ISCC clos-
es with a flag and reverts to One-Bit-Delay mode. The last
zero of the flag, along with the marking line echoed from
the RxD pin, form an EOP for secondary stations further
down the loop.
While the ISCC is actually transmitting a message, the
loop-sending bit in R10 is set to indicate this.
If the Go-Active-On-Poll bit is not set at the time the EOP
passes by, the ISCC cannot send a message until a flag
(terminating the current polling sequence) and another
EOP are received.
If SDLC loop is deselected, the ISCC is designed to exit
from the loop gracefully. When SDLC Loop mode is dese-
lected by writing to WR10; the ISCC waits until the next
polling cycle to remove the one-bit time delay.
If a polling cycle is in progress at the time the command is
written, the ISCC finishes sending any message that it may
be transmitting, ends with an EOP, and disconnects TxD
from RxD. If no message was in progress, the ISCC imme-
diately disconnects TxD from RxD.
Once the ISCC™ is not sending on the loop, an exit from
the loop is accomplished by setting the Loop Mode bit in
WR10 to “0”, and at the same time writing the Abort/Flag
on Underrun and Mark/Flag idle bits with the desired val-
ues. The ISCC will revert to normal SDLC operation as
soon as an EOP is received, or immediately, if the receiver
is already in Hunt mode because of the receipt of an EOP.
4-24
To ensure proper loop operation after the ISCC goes off
the loop, and until the external relays take the ISCC com-
pletely out of the loop, the ISCC should be programmed for
Mark idle instead of Flag idle. When the ISCC goes off the
loop, the On-Loop bit is reset.
Note: With NRZI encoding, removing the stations from
the loop (removing the one-bit time delay) may cause
problems further down the loop because of extraneous
transitions on the line. The ISCC avoids this problem by
making transparent adjustments at the end of each frame
it sends in response to an EOP. A response frame from the
ISCC is terminated by a flag and EOP. Normally, the flag
and the EOP share a zero, but if such sharing would cause
the RxD and TxD pins to be of opposite polarity after the
EOP, the ISCC adds another zero between the flag and
the EOP. This causes an extra line transition so that RxD
and TxD are identical after the EOP is sent. This extra zero
is completely transparent because it only means that the
flag and the EOP no longer share a zero. All that a proper
loop exit needs, therefore, is the removal of the one-bit
delay.
The ISCC allows the user the option of using NRZI in
SDLC Loop mode by programming WR10 appropriately.
With NRZI encoding, the outputs of secondary stations in
the loop may be inverted from their inputs because of mes-
sages that they have transmitted.
The initialization sequence for the SCC cell in SDLC Loop
mode is similar to the sequence used in SDLC mode, ex-
cept that it is somewhat longer. The processor should pro-
gram WR4 first, to select SDLC mode, and then WR10 to
select the CRC preset value and program the Mark/Flag
idle bit. The Loop Mode and Go Active On Poll bits in
WR10 should not be set to “1” yet. The flag is written in
WR7 and the various options are selected in WR3 and
UM011001-0601