LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 97

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the
next clock and will continue driving the SER_IRQ low for a programmable period of three to seven
clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive
the SER_IRQ back high for one clock, then tri-state.
Any SER_IRQ Device (i.e., The LPC47B27x) which detects any transition on an IRQ/Data line for which
it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ
is already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle.
2) Continuous (Idle) Mode : Only the Host controller can initiate a Start Frame to update IRQ/Data line
information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ
will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be
used to stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by
initiating a Start Frame at the end of every Stop Frame.
An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is
defaulted to Continuous mode, therefore only the Host controller can initiate the first Start
Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next
SER_IRQ Cycle’s mode.
SER_IRQ Data Frame
Once a Start Frame has been initiated, the LPC47B27x will watch for the rising edge of the Start Pulse
and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase,
Recovery phase, and Turn-around phase. During the Sample phase the LPC47B27x must drive the
SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is
high, SER_IRQ must be left tri-stated. During the Recovery phase the LPC47B27x must drive the
SER_IRQ high, if and only if, it had driven the SER_IRQ low during the previous Sample Phase. During
the Turn-around Phase the LPC47B27x must tri-state the SER_IRQ. The LPC47B27x will drive the
SER_IRQ line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of
which device initiated the Start Frame.
The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a
number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is
the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock after the rising edge of the Start Pulse).
The SER_IRQ data frame will now support IRQ2 from a logical device, previously SER_IRQ Period 3
was reserved for use by the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the
user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the
user should not configure any logical devices as using IRQ2.
SER_IRQ Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5
(Ser Port 2), and 7 (KBD) shall have IRQ13 as a choice for their primary interrupt.
SMSC LPC47B27x
SER_IRQ PERIOD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
SER_IRQ Sampling Periods
SIGNAL SAMPLED
nIO_SMI/IRQ2
DATASHEET
Not Used
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
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# OF CLOCKS PAST START
11
14
17
20
23
26
29
32
35
38
41
44
47
2
5
8
Rev. 04-17-07