LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 58

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1
is as follows:
The Start, Stop and Parity bits are not included in the word length.
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following table
summarizes the information.
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between
the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of
1s when the data word bits and the parity bit are summed).
SMSC LPC47B27x
MODE
ONLY
BIT 3
FIFO
0
0
BIT 2
IDENTIFICATION
0
0
INTERRUPT
REGISTER
BIT 1
1
0
BIT 0
0
0
PRIORITY
Third
Fourth
LEVEL
BIT 2
BIT 1
0
1
1
1
1
0
0
1
1
Start LSB Data 5-8 bits MSB Parity
INTERRUPT SET AND RESET FUNCTIONS
Transmitter
Holding
Register Empty
MODEM
Status
WORD LENGTH
DATASHEET
INTERRUPT
BIT 0
TYPE
0
1
0
1
Serial Data
5 Bits
6 Bits
7 Bits
8 Bits
-
- 58 -
WORD LENGTH
Transmitter
Holding Register
Empty
Clear to Send or
Data Set Ready or
Ring Indicator or
Data Carrier
Detect
INTERRUPT
5 Bits
6 Bits
7 Bits
8 Bits
Stop
NUMBER OF
SOURCE
STOP BITS
1.5
1
2
2
2
Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter
Holding Register
Reading the
MODEM Status
Register
INTERRUPT
CONTROL
Rev. 04-17-07
RESET