LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 11

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Note:
Note 1: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis
Note 2: The nLPCPD pin may be tied high. The LPC interface will function properly if the nPCI_RESET signal
Note 3: If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the configuration
Note 4. The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and Hard Reset.
Note 5: The IRTX pins (IRTX2/GP35 and GP53/TXD2) are driven low when the part is powered by VTR (VCC=0V
Note 6: The “activate” bit for the CIrCC is reset by VTR POR only. The V
Note 7: The “activate” bit for Serial Port 2 is reset by VTR POR only. The V
Note 8: VTR can be connected to VCC if no wakeup functionality is required.
Note 9: The GP24 /SYSOPT pin requires an external pulldown resistor to put the base IO address for configuration
Note 10: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs
Note 11: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power
SMSC LPC47B27x
The "n" as the first letter of a signal name indicates an "Active Low" signal.
represent multiple buffer types for a single pin function.
follows the protocol defined for the nLRESET signal in the “Low Pin Count Interface Specification”.
register at 0xF0 in Logical Device A that indicates whether or not the 32kHz clock is connected. This bit
determines the clock source for the fan tachometer, LED and “wake on specific key” logic. Set this bit to ‘1’
if the clock is not connected.
with VTR=3.3V). The IRTX2/GP35 pin will remain low following a power-up (VCC POR) until serial port 2 is
enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the
IRCC block. The GP53/TXD2 pin will remain low following a VCC POR until the TXD2 function is selected
for the pin and serial port is enabled by setting the activate bit, at which time the pin will reflect the state of
the IR transmit output of the IRCC block (if IR is enabled).
IRTX2 function is programmed on the GPIO.
the TXD2 function is programmed on the GPIO.
at 0x02E. An external pullup resistor is required to move the base IO address for configuration to 0x04E.
after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the system must
ensure that these pins are high. See Section “Pins That Require External Pullup Resistor”.
PIN
No./
QFP
41
42
43
45
46
47
50
48
49
17
28
General Purpose I/O /
P17
General Purpose I/O /
P16 /nDS1
General Purpose I/O /
P12/nMTR1
General Purpose I/O /
System Option
General Purpose I/O
/MIDI_IN
General Purpose I/O
/MIDI_OUT
General Purpose I/O
/SMI Output
General Purpose I/O /
LED
General Purpose I/O /
LED
General Purpose I/O /
Power Management
Event
General Purpose I/O
/Device Disable Reg.
Control / FDC on
Parallel Port
NAME
DESCRIPTION OF PIN FUNCTIONS
TOTAL
DATASHEET
1
1
1
1
1
1
1
1
1
1
1
GP20/P17
GP21 /P16/
nDS1
GP22 /P12/
nMTR1
GP24
/SYSOPT
GP25
/MIDI_IN
GP26
/MIDI_OUT
GP27
/nIO_SMI
GP60 /LED1
GP61 /LED2
GP42
/nIO_PME
GP43/DDRC
/FDC_PP
- 11 -
SYMBOL
CC
IO8
IO12
IO12
IO8
IO8
IO12
IO12
IO12
IO12
IO12
IO8
BUFFER
TYPE
power-up default for this pin is Logic “0” if the
CC
power-up default for this pin is Logic “0” if
(I/O8/OD8)/
IO8
(I/O12/OD12)/
IO12/(O12/
OD12)
(I/O12/
OD12)/IO12/
(O12/OD12)
(I/O8/OD8)
(I/O8/OD8)/I
(I/O12/OD12)/
O12
(I/O12/OD12)/
OD12
(I/O12/OD12)/
O12
(I/O12/OD12)/
O12
(I/O12/OD12)/
OD12
(I/O8/OD8)/I/I
BUFFER TYPE
FUNCTION
(NOTE 1)
PER
Rev. 04-17-07
9
11
11
NOTE
S