LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 157

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Note 1: A logical device will be active and powered up according to the following equation:
SMSC LPC47B27x
Activate
Default = 0x00
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
Logical Device Control
Logical Device Control
Memory Base Address
I/O Base Address
(see Device Base I/O
Address Table)
Default = 0x00
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
Interrupt Select
Defaults :
0x70 = 0x00 or 0x06
(Note 4)
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
0x72 = 0x00,
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
DMA Channel Select
Default = 0x02 or 0x04
(Note 5)
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
32-Bit Memory Space
Configuration
Logical Device
Logical Device
Configuration
Reserved
LOGICAL DEVICE
REGISTER
Note1, Note 3
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
Note 2
(0xA9-0xDF)
(0xE0-0xFE)
(0x31-0x37)
(0x40-0x5F)
(0x60-0x6F)
(0x76-0xA8)
(0x70,0x72)
(0x71,0x73)
(0x74,0x75)
(0x38-0x3f)
0x60,2,... =
0x61,3,... =
ADDRESS
addr[15:8]
addr[7:0]
(0x30)
0xFF
Table 64 – Logical Device Registers
DATASHEET
Bits[7:1] Reserved, set to zero.
Bit[0]
= 1
= 0
Reserved – Writes are ignored, reads return 0.
Vendor Defined - Reserved - Writes are
ignored, reads return 0.
Reserved – Writes are ignored, reads return 0.
Registers 0x60 and 0x61 set the base address
for the device. If more than one base address
is required, the second base address is set by
registers 0x62 and 0x63.
Refer to Table 58 for the number of base
address registers used by each device.
Unused registers will ignore writes and return
zero when read.
0x70 is implemented for each logical device.
Refer to Interrupt Configuration Register
description. Only the keyboard controller uses
Interrupt Select register 0x72. Unused register
(0x72) will ignore writes and return zero when
read.
compatible).
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Only 0x74 is implemented for FDC, Serial Port
2 and Parallel port. 0x75 is not implemented
and ignores writes and returns zero when read.
Refer to DMA Channel Configuration.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Reserved - not implemented. These register
locations ignore writes and return zero when
read.
Reserved – Vendor Defined (see SMSC
defined
Registers).
Reserved
- 157 -
Interrupts default to edge high (ISA
Activates the logical device currently
selected through the Logical Device #
register.
Logical device currently selected is
inactive
Logical
DESCRIPTION
Device
Configuration
Rev. 04-17-07
STATE
C
C
C
C
C
C
C
C
C
C