LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 194

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Board Test Mode
Board test mode can be entered as follows:
On the rising (deasserting) edge of nPCI_RESET, drive nLFRAME low and drive LAD[0] low.
Exit board test mode as follows:
On the rising (deasserting) edge of nPCI_RESET, drive either nLFRAME or LAD[0] high.
See the “XNOR-Chain Test Mode” section below for a description of this board test mode.
XNOR-CHAIN TEST MODE
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard
during assembly and test operations. See Figure 39 below.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is
activated, the LPC47B27x pin functions are disconnected from the device pins, which all become input
pins except for one output pin at the end of XNOR-Chain.
The tests that are performed when the XNOR-Chain test structure is activated require the board-level
test hardware to control the device pins and observe the results at the XNOR-Chain output pin.
The XNOR-Chain output pin is pin 52, GP31/FAN_TACH1. The nPCI_RESET pin and the power and
ground pins are not included in the XNOR-Chain. See the following subsections for more details.
Introduction
The LPC47B27x provides board test capability through the XNOR chain. When the chip is in the XNOR
chain test mode, setting the state of any of the input pins to the opposite of its current state will cause
the output of the chain to toggle.
All pins on the chip are inputs to the XNOR chain, with the exception of the following:
To put the chip in the XNOR chain test mode, tie LAD0 (pin 20) and nLFRAME (pin 24) low. Then
toggle nPCI_RESET (pin 26) from a low to a high state. Once the chip is put into XNOR chain test
mode, LAD0 (pin 20) and nLFRAME (pin 24) become part of the chain.
To exit the XNOR chain test mode tie LAD0 (pin 20) or nLFRAME (pin 24) high. Then toggle
nPCI_RESET (pin 26) from a low to a high state. A VCC POR will also cause the XNOR chain test
mode to be exited. To verify the test mode has been exited, observe the output at FAN_TACH1 (pin
52). Toggling any of the input pins should not cause its state to change.
SMSC LPC47B27x
I/O#1
1.
2.
3.
4.
VCC (pins 53, 65 & 93), VTR (pin 18), and VREF (pin 44).
VSS (pins 7, 31, 60, & 76) and AVSS (pin 40).
FAN_TACH1 (pin 52). This is the chain output.
nPCI_RESET (pin 26).
I/O#2
FIGURE 39 - XNOR-CHAIN TEST STRUCTURE
APPENDIX - TEST MODE
DATASHEET
I/O#3
- 194 -
I/O#n
Rev. 04-17-07
XNor
Out