LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 156

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Note 1: To allow the selection of the configuration address to a user defined location, these Configuration
The configuration address is only reset to its default address upon a Hard Reset or Vcc POR.
Note: The default configuration address is either 02E or 04E, as specified by the SYSOPT pin.
Logical Device Configuration/Control Registers [0x30-0xFF]
Used to access the registers that are assigned to each logical unit. This chip supports eight logical units
and has eight sets of logical device registers. The eight logical devices are Floppy, Parallel, Serial 1,
Serial 2, Keyboard Controller, game port, Runtime Registers and MPU-401. A separate set (bank) of
control and configuration registers exists for each logical device and is selected with the Logical Device #
Register (0x07).
The INDEX PORT is used to select a specific logical device register. These registers are then accessed
through the DATA PORT.
The Logical Device registers are accessible only when the device is in the Configuration State. The logical
register addresses are shown in the table below.
SMSC LPC47B27x
TEST 6
Default = 0x00, on
VCC POR and
VTR POR
TEST 4
Default = 0x00, on
VCC POR and
VTR POR
TEST 5
Default = 0x00 on
VCC POR and
VTR POR
TEST 1
Default = 0x00, on
VCC POR and
VTR POR
TEST 2
Default = 0x00, on
VCC POR and
VTR POR
TEST 3
Default = 0x00, on
VCC POR and
VTR POR
REGISTER
Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that
is, the address must be on an even byte boundary. As soon as both bytes are changed, the
configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte
1; writing CR27 changes the base address).
ADDRESS
0x2C R/W
0x2A R/W
0x2B R/W
0x2D R/W
0x2E R/W
0x2F R/W
Table 63 – Chip Level Registers (cont’d)
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired results.
Bit[7] Test Mode: Reserved for SMSC. Users
should not write to this bit, may produce undesired
results.
Bit[6] 8042 Reset:
1 = Put the 8042 into reset
0 = Take the 8042 out of reset
Bits[5:0] Test Mode: Reserved for SMSC. Users
should not write to this bit, may produce undesired
results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired results.
DATASHEET
- 156 -
DESCRIPTION
Rev. 04-17-07
STATE
C
C
C
C
C