LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 79

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

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Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle.
EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable
transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for
low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers
permits the use of adaptive signal timing Peer-to-peer capability.
Vocabulary
The following terms are used in this document:
assert:
forward: Host to Peripheral communication.
reverse: Peripheral to Host communication
Pword: A port word; equal in size to the width of the LPC interface. For this implementation, PWord is
1:
0:
SMSC LPC47B27x
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
SIGNAL
The host initiates an I/O read cycle to the selected EPP register.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the
nWRITE signal is valid.
If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts
nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the
termination phase of the cycle.
The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
EPP
For correct EPP read cycles, PCD is required to be a low.
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a
"false" state.
always 8 bits.
A high level.
A low level.
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
nAddress
Strobe
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Status
Error
EPP NAME
TYPE
I/O
O
O
O
O
Table 40 - EPP Pin Descriptions
I
I
I
I
I
This signal is active low. It denotes a write operation.
through with no inversion, Same as SPP).
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is
ready for the next transfer.
operation.
is reset to its initial operational mode.
write operation.
Same as SPP mode.
Same as SPP mode.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
This signal is active low.
This signal is active low. It is used to denote data read or write
This signal is active low. When driven active, the EPP device
This signal is active low. It is used to denote address read or
Same as SPP mode.
DATASHEET
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EPP DESCRIPTION
It is driven inactive as a positive
Rev. 04-17-07