LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 65

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

REGISTER
ADDRESS
ADDR = 0
ADDR = 0
ADDR = 1
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
SMSC LPC47B27x
DLAB = 0
DLAB = 0
DLAB = 0
DLAB = 1
DLAB = 1
(Note 1)
TABLE 4 – REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write Only)
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Scratch Register (Note 5)
Divisor Latch (LS)
Divisor Latch (MS)
REGISTER NAME
REGISTER
SYMBOL
(Note 8)
MCR
MSR
RBR
THR
FCR
SCR
DLM
LCR
LSR
DDL
IER
- 65 -
IIR
RCVR FIFO
Access Bit
Data Bit 7
Data Bit 7
Enabled
(Note 6)
(Note 6)
(DLAB)
Error in
Trigger
Divisor
Carrier
RCVR
Detect
(DCD)
BIT 7
FIFOs
Latch
Bit 15
MSB
Data
Bit 7
Bit 7
DATASHEET
0
0
Trigger LSB
Transmitter
Data Bit 6
Data Bit 6
Set Break
Indicator
Enabled
(Note 6)
(TEMT)
(Note 3)
BIT 6
FIFOs
RCVR
Empty
Bit 14
Ring
Bit 6
Bit 6
(RI)
0
0
Rev. 04-17-07
Stick Parity
Transmitter
Data Bit 5
Data Bit 5
Reserved
Data Set
Register
Holding
(THRE)
Ready
BIT 5
(DSR)
Bit 13
Bit 5
Bit 5
0
0
0
Send (CTS)
Even Parity
Data Bit 4
Data Bit 4
Reserved
Interrupt
Clear to
BIT 4
Select
(EPS)
Break
Bit 12
Loop
Bit 4
Bit 4
(BI)
0
0
Interrupt ID
DMA Mode
Bit
Delta Data
Data Bit 3
Data Bit 3
Error (FE)
MODEM
Interrupt
Framing
(DDCD)
(Note 7)
(Note 4)
Enable
(EMSI)
Enable
Carrier
Status
Select
Detect
BIT 3
(PEN)
OUT2
Parity
Bit 11
Bit 3
(Note 6)
Bit 3
XMIT FIFO
Number of
Edge Ring
Data Bit 2
Data Bit 2
Error (PE)
Stop Bits
Receiver
Indicator
Interrupt
Interrupt
(Note 4)
Trailing
Enable
(TERI)
BIT 2
Status
(ELSI)
OUT1
Reset
(STB)
Parity
Bit 10
ID Bit
Bit 2
Bit 2
Line
FIFO Reset
Send (RTS)
Transmitter
Interrupt ID
Select Bit 1
Request to
Error (OE)
Delta Data
Set Ready
Data Bit 1
Data Bit 1
(ETHREI)
Register
Interrupt
Overrun
Holding
(DDSR)
(WLS1)
Enable
Length
Empty
RCVR
BIT 1
Word
Bit 1
Bit 1
Bit 9
Bit
Word Length
Ready (DTR)
FIFO Enable
Data Ready
Select Bit 0
Delta Clear
Data Bit 0
Data Bit 0
Received
Available
Terminal
Interrupt
(ERDAI)
Interrupt
Pending
(Note 2)
to Send
(WLS0)
(DCTS)
Enable
BIT 0
Data
Data
(DR)
“0” if
Bit 0
Bit 0
Bit 8