LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 129

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Note 1: This register contains some bits that are read or write only.
Note 2: Bit 0 is not cleared by HARD RESET.
Note 3: This register is read-only when GP43 register bit [3:2] = 01 and the GP43 pin is high.
Note 4: Bits [3:2] of this register are reset (cleared) on VCC POR and Hard Reset (and VTR POR).
Note 5: Bit 3 of this register is reset (cleared) on VCC POR and Hard Reset (and VTR POR).
Note 6: The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared.
Note 7: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register
The following registers are located at an offset from (PME_BLK) the address programmed into the base
I/O address register for Logical Device A.
SMSC LPC47B27x
PME_STS
Default = 0x00
on VTR POR
N/A
PME_EN
Default = 0x00
on VTR POR
N/A
REGISTER
OFFSET
60-7F
(hex)
5C
5D
5E
5F
NAME
may be set on a VCC POR. If GP32, GP33 and GP53 are configured as input, then their
corresponding PME and SMI status bits will be set on a VCC POR. These GPIOs cannot be
used for PME wakeup when the part is under VTR power (VCC=0).
TYPE
R/W
R/W
R/W
R/W
R
REG OFFSET
RESET
HARD
(R/W)
(R/W)
(hex)
Table 60 - Runtime Register Description
-
-
-
-
-
(R)
(R)
00
01
02
03
VCC
POR
DATASHEET
-
-
-
-
-
Bit[0] PME_Status
= 0 (default)
= 1 Set when LPC47B27x would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or
HARD RESET.
Writing a “1” to PME_Status will clear it and cause the
LPC47B27x to stop asserting nIO_PME, in enabled.
Writing a “0” to PME_Status has no effect.
Reserved – reads return 0
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or
HARD RESET
Reserved – reads return 0
nIO_PME signal, independent of the state of the
PME_En bit.
VTR POR
nIO_PME signal assertion is disabled (default)
Enables LPC47B27x to assert nIO_PME signal
- 129 -
0x00
0x00
0x00
0x00
-
RESET
SOFT
-
-
-
-
-
DESCRIPTION
Fan2 Preload Register
LED1
LED2
Keyboard Scan Code
Reserved – reads return 0
REGISTER
Rev. 04-17-07