LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 160

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Note:
Note:
Note:
Note:
Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note:
Note:
Note 1: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for
Note A. Logical Device IRQ and DMA Operation
1.
disabled by a register bit in that logical block, the IRQ and/or DMA channel must be disabled. This is in
addition to the IRQ and DMA channel disabled by the Configuration Registers (active bit or address not
valid).
a.
b.
c.
SMSC LPC47B27x
DMA Channel
Select
Default=0x02 or
0x04
on VCC POR,
VTR POR,
HARD RESET
and
SOFT RESET
NAME
(Note 1)
nSMI must be disabled to use IRQ2.
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero
value AND :
IRQs are disabled if not used/selected by any Logical Device. Refer to Note A.
All IRQ’s are available in Serial IRQ mode.
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
For the UART 2 logical device, by setting the DMA Enable bit. Refer to the IrCC specification.
DMA channels are disabled if not used/selected by any Logical Device. Refer to Note A.
logical device 3 and 5 is 0x04.
IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is
FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled.
Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".
The FDC is in power down (disabled).
Serial Ports:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port
interrupt is disabled.
Disabling DMA Enable bit, disables DMA for UART2. Refer to the IrCC specification.
Parallel Port:
I.
ii.
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
For the Serial Port logical device by setting any combination of bits D0-D3 in the IER
For the KYBD by (refer to the KYBD controller section of this spec).
For MPU-401 logical device (refer to the MPU-401 section of this spec).
Table 67 - DMA Channel Select Configuration Register Description
(FROM ECR REGISTER)
and by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is
disabled.
ECP Mode:
(1)
(2)
000
001
REG INDEX
0x74 (R/W)
MODE
(DMA) dmaEn from ecr register. See table.
IRQ - See table.
PRINTER
Bits[2:0] select the DMA Channel.
SPP
DATASHEET
0x00= Reserved
0x01= DMA1
0x02= DMA2
0x03= DMA3
0x04-0x07= No DMA active
CONTROLLED BY
- 160 -
IRQE
IRQE
DEFINITION
IRQ
CONTROLLED BY
dmaEn
dmaEn
DMA
Rev. 04-17-07
STATE
C