LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 107

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

KDAT and MDAT signals cannot be isolated internal to the part. This causes an IO_PME# to be
generated if the keyboard and/or mouse PME events are enabled. Note that the keyboard and mouse
isolation bits only prevent the internal 8042 in the part from setting these status bits.
Case 1: Keyboard and/or Mouse Powered by VTR
The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are
powered by VTR. In this case, an IO_PME# will not be generated, since the keyboard and mouse PME
enable bits are reset to zero on a VTR POR. The BIOS software needs to clear these PME status bits
after power-up.
Case 2: Keyboard and/or Mouse Powered by VCC
The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are
powered by VCC. In this case, an IO_PME# will be generated if the enable bits were set for wakeup,
since the keyboard and mouse PME enable bits are VTR powered. Therefore, if the keyboard and
mouse are powered by VCC, the enable bits for keyboard and mouse events should be cleared prior to
entering a sleep state where VCC is removed (i.e., S3) to prevent a false PME from being generated. In
this case, the keyboard and mouse should only be used as PME and/or wake events from the S0 and/or
S1 states. The BIOS software needs to clear these PME status bits after power-up.
SMSC LPC47B27x
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Rev. 04-17-07
DATASHEET