LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 111

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Note:
functionality: P12, P16, P17 and game port x-axis and y-axis inputs (J1X, J1Y, J2X, J2Y).
When a GPIO port is programmed as an input, reading it through the GPIO data register latches either
the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is
programmed as an input has no effect (Table 57).
When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been
written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is
programmed as an output returns the last value written to the data register (Table 57). When the GPIO
is programmed as an output, the pin is excluded from the PME and SMI logic.
The LPC47B27x provides 31 GPIOs that can directly generate a PME. See the table in the next
section. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set
the associated status bit in the PME_STS 2 register. The default is the low-to-high edge. If the
corresponding enable bit in the PME_EN 2 register and the PME_EN bit in the PME_EN register is set,
a PME will be generated. These registers are located in the PME_BLK of runtime registers which are
located at the address contained in the configuration registers 0x60 and 0x61 in Logical Device A. The
PME status bits for the GPIOs are cleared on a write of ‘1’. In addition, the LPC47B27x provides 19
GPIOs that can directly generate an SMI. See the table in the next section.
GPIO PME and SMI Functionality
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and
enable registers:
SMSC LPC47B27x
GPx_nIOW
GPx_nIOR
OPERATION
WRITE
HOST
READ
When the following functions are selected, the associated GPIO pins have bi-directional
GP10-GP17
GP20-GP22, GP24-GP27
GP30-GP33
GP41, GP43
GP50-GP57
SD-bit
Data Register
Transparent
D-TYPE
D
Q
Bit-n
GPIO
LATCHED VALUE OF GPIO PIN
NO EFFECT
Q
D
GPIO INPUT PORT
TABLE 57 - GPIO Read/Write Behavior
0
1
DATASHEET
- 111 -
LAST WRITE TO GPIO DATA REGISTER
BIT PLACED IN GPIO DATA REGISTER
GPIO
Configuration
Register bit-1
(Polarity)
GPIO OUTPUT PORT
GPIO
Configuration
Register bit-0
(Input/Output)
Rev. 04-17-07
GPIO
PIN