LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 147

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

SMSC LPC47B27x
WDT_CTRL
Default = 0x00
on VTR POR
FAN1
Default = 0x00
FAN2
Default = 0x00
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(R/W)
(hex)
55
56
57
DATASHEET
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
=1
=0
Bit[1] Reserved
Bit[2] Force Timeout, W
=1
Bit[3] P20 Force Timeout Enable, R/W
= 1
Controller, to force the WD timeout event. A WD timeout
event may still be forced by setting the Force Timeout Bit, bit
2.
= 0
Note: The P20 signal will remain high for a minimum of 1us
and can remain high indefinitely. Therefore, when P20
forced timeouts are enabled, a self-clearing edge-detect
circuit is used to generate a signal which is ORed with the
signal generated by the Force Timeout Bit.
Bit[7:4] Reserved. Set to 0
FAN Register 1
Bit[0] Fan Control
Bit[6:1] Duty Cycle Control for FAN1
Control the duty cycle of the FAN1 pin
Bit[7] Fan 1 Clock Select
This bit is used with the Fan 1 Clock Source Select and the
Fan 1 Clock Multiplier bits in the Fan Control register
(0x58) to determine the fan speed F
Modes for Fan” table in “Fan Speed Control and
Monitoring” section.
The fan speed may be doubled through bit 2 of Fan
Control Register at 0x58.
FAN Register 2
Bit[0] Fan Control
Bit[6:1] Duty Cycle Control for FAN2
Control the duty cycle of the FAN2 pin
Bit[7] Fan 2 Clock Select
This bit is used with the Fan 2 Clock Source Select and
the Fan 2 Clock Multiplier bits in the Fan Control register
(0x58) to determine the fan speed F
Modes for Fan” in “Fan Speed Control and Monitoring”
section.
The fan speed may be doubled through bit 3 of Fan
Control Register at 0x58.
- 147 -
WD timeout occurred
WD timer counting
Forces WD timeout event; this bit is self-clearing
Allows rising edge of P20, from the Keyboard
P20 activity does not generate the WD timeout
event.
1=FAN1 pin is high
0=bits[6:1] control the duty cycle of the
FAN1 pin.
000000 = pin is low
100000 = 50% duty cycle
111111 = pin is high for 63, low for 1
1=FAN2 pin is high
0=bits[6:1] control the duty cycle of the
FAN2 pin.
000000 = pin is low
100000 = 50% duty cycle
111111 = pin is high for 63, low for 1
DESCRIPTION
OUT
OUT
. See “Different
. See “Different
Rev. 04-17-07