LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 27

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of
either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which
corresponds to the default precompensation setting and 250 Kbps.
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data
rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.
BIT 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7
shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track
number to start precompensation. this starting track number can be changed by the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and
data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset
or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.
Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime
register block.
SMSC LPC47B27x
RESET
COND.
DRT1
DRIVE RATE
RESET
0
0
0
0
0
0
0
0
1
S/W
7
0
DRT0
PRECOMP
POWER
DOWN
0
0
0
0
1
1
1
1
0
432
111
001
010
011
100
101
110
000
6
0
SEL1
DATA RATE
1
0
0
1
1
0
0
1
1
Table 7 - Precompensation Delays
5
0
0
SEL0
1
0
1
0
1
0
1
0
1
DATASHEET
COMP2
Default: See Table 10
Table 8 - Data Rates
PRE-
PRECOMPENSATION DELAY (nsec)
4
0
<2Mbps
125.00
166.67
208.33
250.00
Default
41.67
83.34
1Meg
1Meg
1Meg
0.00
MFM
500
300
250
500
500
250
DATA RATE
- 27 -
COMP1
PRE-
3
0
250
150
125
250
250
125
FM
---
---
---
COMP0
PRE-
2
0
DENSEL
1
1
0
0
1
1
0
0
1
2Mbps
Default
DRATE
104.2
SEL1
20.8
41.7
62.5
83.3
125
0
1
1
DRATE
Rev. 04-17-07
SEL0
DRATE(1)
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1