LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 154

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

SMSC LPC47B27x
Config Control
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
Logical Device #
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and
HARD RESET
Card Level Reserved 0x08 - 0x1F Reserved - Writes are ignored, reads return 0 .
Device ID -
Hard wired
Default = 0x51
on VCC POR,
VTR POR,
SOFT RESET and
HARD RESET
Device Rev
Hard wired
= Current Revision
PowerControl
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and
HARD RESET
REGISTER
0x03 - 0x06 Reserved - Writes are ignored, reads return 0 .
ADDRESS
0x07 R/W
0x22 R/W
0x02 W
0x20 R
0x21 R
0x00 -
0x01
Chip (Global) Control Registers
Table 63 - Chip Level Registers
Chip Level, SMSC Defined
Reserved - Writes are ignored, reads return 0.
The hardware automatically clears this bit after the
write, there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to the "Configuration
Registers" table for the soft reset value for each
register.
A write to this register selects the current logical
device.
configuration registers for each logical device. Note:
The Activate command operates only on the selected
logical device.
A
identification. Bits[7:0] = 0x51 when read.
A read only register which provides device revision
information. Bits[7:0] = current revision when read.
Bit[0] FDC Power
Bit[1] Reserved
Bit[2] Game Port Power
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power (Note 1)
Bit[6] MPU-401 Power
For each bit above (except Reserved)
= 0
= 1
Bit[7] PME Power (Note 1)
= 0
= 1
DATASHEET
read
Power Off or Disabled
Power On or Enabled
Trickle Clock Inactive (default)
Trickle Clock Running.
internal PWRGOOD signal.
This allows access to the control and
only
- 154 -
register
DESCRIPTION
which
provides
PLL selected by
device
Rev. 04-17-07
STATE
C
C
C
C
C