LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 165

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

SMSC LPC47B27x
CLOCKI32
Default = 0x00
on VTR POR
FDC_PP
Default = 0x00
on VTR POR
MPU-401 Primary
Base I/O Address
High Byte
Default = 0x03
on HARD RESET,
SOFT RESET, VCC
POR and VTR POR
MPU-401 Primary
Base I/O Address
Low Byte
Default = 0x30
on HARD RESET,
NAME
NAME
NAME
Table 72 - KYBD, Logical Device 7 [Logical Device Number = 0x07]
0xF1 - 0xFF
REG INDEX
REG INDEX
REG INDEX
Table 74 – MPU-401 [Logical Device Number = 0x0B]
0x60 R/W
0x61 R/W
(R/W)
(R/W)
0xF1
0xF0
Table 73 - PME, Logical Device A
Bit[3] KLATCH
(default)
Bit[2] Port 92 Select
Bit[1] Reserved
Bit[0] Reserved
Reserved - read as ‘0’
= 1 MINT is the latched 8042 MINT
= 0 KINT is the 8042 KINT ANDed with Latched KINT
= 1 KINT is the latched 8042 KINT
Bit[0] (CLK32_PRSN)
Bit[1] SPEKEY_EN. This bit is used to turn the logic
for the “wake on specific key” feature on and off. It will
disable the 32kHz clock input to the logic when turned
off. The logic will draw no power when disabled.
Bits[7:2] are reserved
Bit[1:0]
00 = Bits in PP mode Register control the FDC on the
parallel port, the FDC_PP pin function is not used.
01 = The FDC_PP pin controls the FDC on the PP as
follows: (non-inverted polarity) when the pin is low, the
parallel port pins are used for a floppy disk controller:
drive 0 is on FDC pins, drive 1 is on parallel port pins
10 = The FDC_PP pin controls the FDC on the PP as
follows: (non-inverted polarity) when the pin is low, the
parallel port pins are used for a floppy disk controller:
drive 0 is on parallel port pins and drive 1 is on parallel
port pins
11 = Reserved
Bits[7:2] Reserved
= 0 Port 92 Disabled
= 1 Port 92 Enabled
Bit[0] A8
Bit[1] A9
Bit[2] A10
Bit[3] A11
Bit[4] “0”
Bit[5] “0”
Bit[6] “0”
Bit[7] “0”
Bit[0] “0”
Bit[1] A1
Bit[2] A2
Bit[3] A3
Bit[4] A4
Bit[5] A5
DATASHEET
on (default)
0=32kHz clock is connected to the CLKI32
pin (default)
1=32kHz clock is not connected to the CLKI32
pin (pin is grounded)
0= “Wake on specific key” logic is
1= “Wake on specific key” logic is off
- 165 -
DEFINITION
DEFINITION
DEFINITION
Rev. 04-17-07
STATE
STATE
STATE
C
C
C
C