LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 29

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

DATA REGISTER (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data and result status are transferred between the host processor and the
floppy disk controller through the Data Register.
Data transfers are governed by the RQM and DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode after any form of reset.
compatibility. The default values can be changed through the Configure command (enable full FIFO operation with
threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk
error. Table 11 gives several examples of the delays with a FIFO.
The data is based upon the following formula:
At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the
RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that
invalid data is not transferred.
An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current
sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result
phase may be entered.
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
SMSC LPC47B27x
Threshold # x
RESET
COND.
DATA RATE
1
CHG
DSK
N/A
7
x 8
FIFO THRESHOLD
FIFO THRESHOLD
FIFO THRESHOLD
- 1.5 µs = DELAY
EXAMPLES
EXAMPLES
EXAMPLES
N/A
15 bytes
15 bytes
15 bytes
6
0
2 bytes
8 bytes
2 bytes
8 bytes
2 bytes
8 bytes
1 byte
1 byte
1 byte
N/A
5
0
Table 11 - FIFO Service Delay
DATASHEET
N/A
4
0
1 x 4 µs - 1.5 µs = 2.5 µs
2 x 4 µs - 1.5 µs = 6.5 µs
8 x 4 µs - 1.5 µs = 30.5 µs
15 x 4 µs - 1.5 µs = 58.5 µs
1 x 8 µs - 1.5 µs = 6.5 µs
2 x 8 µs - 1.5 µs = 14.5 µs
8 x 8 µs - 1.5 µs = 62.5 µs
15 x 8 µs - 1.5 µs = 118.5 µs
1 x 16 µs - 1.5 µs = 14.5 µs
2 x 16 µs - 1.5 µs = 30.5 µs
8 x 16 µs - 1.5 µs = 126.5 µs
15 x 16 µs - 1.5 µs = 238.5 µs
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
- 29 -
N/A
500 Kbps DATA RATE
3
0
2 Mbps DATA RATE
1 Mbps DATA RATE
N/A
2
0
N/A
1
0
This maintains PC/AT hardware
N/A
0
0
Rev. 04-17-07