LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 130

• Manufacturer Part Number: LPC47B272-MS
• Description: IC CTRLR SUPER I/O LPC 100-QFP
• Manufacturer: SMSC

Specifications of LPC47B272-MS

• Controller Type: I/O Controller
• Interface: LPC
• Voltage - Supply: 3.3V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1019

SMSC LPC47B27x
PME_STS1
Default = 0x00
PME_STS2
Default = 0x00
PME_STS3
Default = 0x00
on VTR POR
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(R/W)
(hex)
04
05
06
DATASHEET
PME Wake Status Register 1
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or
the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] CIR
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit
in PME Wake Status Register has no effect.
PME Wake Status Register 2
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or
the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit
in PME Wake Status Register has no effect.
PME Wake Status Register 3
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or
the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_STS (status of group SMI signal for PME)
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP27
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit
in PME Wake Status Register has no effect.
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DESCRIPTION
Rev. 04-17-07