LPC47B272-MS SMSC, LPC47B272-MS Datasheet - Page 155
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LPC47B272-MS
Manufacturer Part Number
LPC47B272-MS
Description
IC CTRLR SUPER I/O LPC 100-QFP
Manufacturer
SMSC
Datasheet
1.LPC47B272-MS.pdf
(195 pages)
Specifications of LPC47B272-MS
Controller Type
I/O Controller
Interface
LPC
Voltage - Supply
3.3V
Current - Supply
15mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1019
Available stocks
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Manufacturer
Quantity
Price
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ADI
Quantity:
957
Company:
Part Number:
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Manufacturer:
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SMSC LPC47B27x
Power Mgmt
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
OSC
Default = 0x04, on
on VCC POR,
VTR POR and
HARD RESET
Chip Level
Vendor Defined
Configuration
Address Byte 0
Default
=0x2E (Sysopt=0)
=0x4E (Sysopt=1)
on VCC POR and
HARD RESET
Configuration
Address Byte 1
Default = 0x00
on VCC POR and
HARD RESET
Default = 0x00
on VCC POR,
SOFT RESET and
HARD RESET
Chip Level
Vendor Defined
Note 1:
REGISTER
REGISTER
CR22 Bit 5 and Bit 7 are reset by VTR POR only.
ADDRESS
ADDRESS
0x23 R/W
0x24 R/W
0x25
0x26
0x27
0x28
0x29
Table 63 – Chip Level Registers (cont’d)
Bit[0] FDC (see not in the “FDC Power Management”
section)
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6] MPU-401
Bit[7] Reserved (read as 0)
For each bit above (except Reserved)
= 0
= 1
Bit[0] Reserved
Bit [1] PLL Control
= 0
= 1
Bits[3:2] OSC
= 01
= 10
= 00
= 11
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0
= 1
Note: For normal operation, bit 6 should be set.
Bit[7] Reserved
Reserved - Writes are ignored, reads return 0.
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
See Note 1
Bit[7:0] Configuration Address Bits [15:8]
See Note 1
Bits[7:0] Reserved - Writes are ignored, reads return
0.
Reserved - Writes are ignored, reads return 0.
DATASHEET
Intelligent Pwr Mgmt off
Intelligent Pwr Mgmt on
Osc is on, BRG clock is on.
Same as above (01) case.
Osc is on, BRG Clock Enabled.
Osc is off, BRG clock is disabled.
12-Bit Address Qualification
16-Bit Address Qualification
PLL is on (backward Compatible)
PLL is off
- 155 -
DESCRIPTION
DESCRIPTION
Rev. 04-17-07
STATE
STATE
C
C
C
C
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