AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 99

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

5
LAPPEN
When DXSUFLO is set to ZERO,
the transmitter is turned off when
an UFLO error occurs (CSR0,
TXON = 0).
When DXSUFLO is set to ONE,
the
gracefully recovers from an
UFLO error. It scans the transmit
descriptor ring until it finds the
start of a new frame and starts a
new transmission.
Read/Write accessible always.
DXSUFLO is cleared by asserting
the RESET pin or reading the
Reset register and is not affected
by STOP.
Look Ahead Packet Processing
(LAPPEN). When set to a one,
the LAPPEN bit will cause the
PCnet-ISA II controller to gener-
ate an interrupt following the
descriptor write operation to the
first buffer of a receive packet.
This interrupt will be generated
in addition to the interrupt that is
generated following the descrip-
tor write operation to the last
buffer of a receive packet. The
interrupt will be signaled through
the RINT bit of CSR0.
Setting LAPPEN to a one also
enables the PCnet-ISA II con-
troller to read the STP bit of the
receive descriptors. PCnet-ISA
II controller will use STP infor-
mation to determine where it
should begin writing a receive
packet’s data. Note that while in
this mode, the PCnet-ISA II con-
troller can write intermediate
packet data to buffers whose
descriptors do not contain STP
bits set to one. Following the
write to the last descriptor used
by a packet, the PCnet-ISA II
controller will scan through the
next descriptor entries to locate
the next STP bit that is set to a
one. The PCnet-ISA II controller
will begin writing the next pack-
et’s data to the buffer pointed to
by that descriptor.
Note
descriptors may be allocated by
the host for each packet, and not
all messages may need all of the
descriptors that are allocated
between descriptors that contain
STP = one, then some descrip-
tors/buffers may be skipped in
the ring. While performing the
PCnet-ISA
that
because
II
controller
several
Am79C961A
4
3
DXMT2PD
EMBA
search for the next STP bit that
is set to one, the PCnet-ISA II
controller will advance through
the
regardless of the state of owner-
ship bits. If any of the entries that
are examined during this search
indicate OWN = one, PCnet-ISA
II will RESET the OWN bit to
zero in these entries. If a
scanned entry indicates host
ownership with STP=“0", then
the PCnet-ISA II controller will
not alter the entry, but will
advance to the next entry.
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the PCnet-ISA II controller, then
the PCnet-ISA II controller will
stop advancing through the ring
entries and begin periodic poll-
ing of this entry. When the STP
bit is found to be true, and the
descriptor that contains this set-
ting is owned by the PCnet-ISA II
controller, then the PCnet-ISA II
controller will stop advancing
through the ring entries, store
the descriptor information that is
has just read, and wait for the
next receive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
“header” portion of a receive
packet will always be written to a
particular memory area, and the
“data” portion of a receive pack-
et will always be written to a sep-
arate memory area. The inter-
rupt is generated when the
“header” bytes have been writ-
ten to the “header” memory
area.
Read/Write accessible always.
The LAPPEN bit will be reset
zero
unaffected by the STOP. See
Appendix E for more information
on LAPP.
Disable
Deferral.
Media
section). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
DXMT2PD is cleared by RESET
and is not affected by STOP.
Enable Modified Back-off Algo-
rithm. If EMBA is set, a modified
receive
by
Access
Transmit
(Described
RESET
descriptor
Management
Two
and
in
Part
ring
will
the
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