AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 121

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

RDRA and TDRA
TDRA and RDRA indicate where the transmit and
receive descriptor rings, respectively, begin. Each DRE
must be located on an 8-byte boundary.
LADRF
The Logical Address Filter (LADRF) is a 64-bit mask
that is used to accept incoming Logical Addresses. If
the first bit in the incoming address (as transmitted on
the wire) is a “1", the address is deemed logical. If the
first bit is a “0", it is a physical address and is compared
against the physical address that was loaded through
the initialization block.
A logical address is passed through the CRC genera-
tor, producing a 32-bit result. The high order 6 bits of
the CRC are used to select one of the 64 bit positions
in the Logical Address Filter. If the selected filter bit is
set, the address is accepted and the frame is placed
into memory.
The Logical Address Filter is used in multicast addressing
schemes. The acceptance of the incoming frame based
on the filter value indicates that the message may be
intended for the node. It is the node’s responsibility to
determine if the message is actually intended for the node
by comparing the destination address of the stored mes-
sage with a list of acceptable logical addresses.
If the Logical Address Filter is loaded with all zeroes
and promiscuous mode is disabled, all incoming logical
addresses except broadcast will be rejected.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is handled as
follows:
.
MATCH = 1: Packet Accepted
MATCH = 0: Packet Rejected
47
Destination Address
Received Message
1 0
1
Address Match Logic
SEL
GEN
CRC
Am79C961A
7. If the Disable Broadcast Bit is cleared, the
8. If the Disable Broadcast Bit is set and promiscuous
9. If the Disable Broadcast Bit is set and promiscous
If external loopback is used, the FCS logic must be
allocated to the receiver (by setting the DXMTFCS bit
in CSR15, and clearing the ADD_FCS bit in TMD1)
when using multicast addressing.
PADR
This 48-bit value represents the unique node address
assigned by the IEEE and used for internal address
comparison. PADR[0] is the first address bit transmit-
ted on the wire, and must be zero. The six-hex-byte no-
menclature used by the IEEE maps to the PCnet-ISA II
controller PADR register as follows: the first byte com-
prises PADR[7:0], with PADR[0] being the least signifi-
cant bit of the byte. The second IEEE byte maps to
PADR[15:8], again from LSbit to MSbit, and so on. The
sixth byte maps to PADR[47:40], the LSbit being
PADR[40].
MODE
The mode register in the initialization block is copied
into CSR15 and interpreted according to the descrip-
tion of CSR15.
31
broadcast address is accepted.
mode is enabled, the broadcast address is
accepted.
mode is disabled, the broadcast address is
rejected.
32-Bit Resultant CRC
64
6
26
63
MUX
(LADRF)
Address
Logical
Filter
0
MATCH
0
19364B-23
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