AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 120

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

0
ISACSR8: Software Configuration Register
(Read-Only Register)
ISACSR9: Miscellaneous Configuration 2
Bit
1
0
120
15-12
11-8
Bit
7-4
2-0
3
COL E
AUIFD
FDEN
Name
Description
Read-only image of SRAM(3:0) of PnP register
0x48-0x49.
Read-only image of BPAM(3:0) of PnP register
0x40-0x41.
Read-only image of IRQSEL(3:0) of PnP
register 0x70.
Read only bit indicating whether the SRAM is
activated as a memory resource. Set when the
Shared Memory is not activated as an ISA
memory resource.
Read-only image of DMASEL(2:0) of PnP
register 0x74.
Enable Collision Signal. Indi-
cates collision activity on the
network.
0 disables the signal, 1 enables
the signal.
AUI Full Duplex. AUIFD controls
whether Full Duplex operation
on the AUI port is enabled.
AUIFD is only meaningful if
FDEN (ISACSR9, bit 0) is set to
ONE. If the FDEN bit is ZERO,
the AUI port will always operate
in Half Duplex mode. In addition,
if FDEN is set to ONE but the
AUIFD bit is reset to ZERO, the
AUI port will always operate in
Half Duplex mode. If FDEN is set
to ONE and AUIFD is set to
ONE, Full Duplex operation on
the AUI port is enabled.
AUIFD is read/write accessible
always. It is reset to ZERO by
the RESET pin, and is unaffect-
ed by reading the Reset register
or setting the STOP bit.
Full Duplex Enable. FDEN con-
trols whether Full Duplex opera-
tion is enabled. When FDEN is
cleared, Full Duplex operation
is not enabled and the PC-
net-ISA II will always operate in
the Half Duplex mode. When
FDEN is set, the PCnet-ISA II
will operate in Full Duplex mode
when the 10BASE-T or GPSI
port is enabled or when the AUI
port is enabled and the AUIFD
(ISACSR9, bit 1) bit is set. Note
Description
Am79C961A
Initialization Block
The figure below shows the Initialization Block memory
configuration. Note that the Initialization Block must be
based on a word (16-bit) boundary.
RLEN and TLEN
The TLEN and RLEN fields in the initialization block are
3 bits wide, occupying bits 15,14, and 13, and the value
in these fields determines the number of Transmit and
Receive Descriptor Ring Entries (DRE) which are used
in the descriptor rings. Their meaning is as follows:
If a value other than those listed in the above table is
desired, CSR76 and CSR78 can be written after initializa-
tion is complete. See the description of the appropriate
CSRs.
IADR+00
IADR+02
IADR+04
IADR+06
IADR+08
IADR+10
IADR+12
IADR+14
IADR+16
IADR+18
IADR+20
IADR+22
Address
R/TLEN
000
001
010
011
100
101
110
111
15–12
RLEN
TLEN
Bits
that Full Duplex operation will
not
10BASE-T
(CSR15, bit 12) is set.
FDEN is read/write accessible
always. It is reset to ZERO by
the RESET pin, and is unaffect-
ed by reading the Reset register
or setting the STOP bit.
11–8
RES
RES
Bits
TDRA 15–00
PADR 31–16
PADR 15–00
PADR 47–32
MODE 15–00
LADRF 15–00
RDRA 15–00
LADRF 31–16
LADRF 47–32
LADRF 63–48
be
enabled
port
# of DREs
Bits
7–4
RDRA 23–16
TDRA 23–16
128
16
32
64
1
2
4
8
if
DLNKST
on
Bits
3–0
the