AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 111

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

CSR84-85: DMA Address
Bit
31-0
CSR86: Buffer Byte Counter
Bit
15-12
11-0 DMABC
DMABA
Name
Name
RES
The DMABAT register is unde-
fined until written.
When the Bus Activity Timer
register (CSR82: DMABAT) is
enabled, the PCnet-ISA II con-
troller will relinquish the bus
when either the time specified in
DMABAT has elapsed or the
number of transfers specified in
DMABR have occurred or no
more pending operation left to
be performed. When ENTST
(CSR4.15) is asserted, all writes
to this register will automatically
perform a decrement cycle.
Read/write
when STOP or SPND bits are
set.
DMA Address Register.
This register contains the address
of system memory for the current
DMA cycle. The Bus Interface
Unit controls the Address Register
by issuing increment commands
to increment the memory address
for sequential operations. The
DMABA register is undefined until
the first PCnet-ISA II controller
DMA operation.
This register has meaning only if
the PCnet-ISA II controller is in
Bus Master Mode.
Read/write
when STOP or SPND bits are
set.
Reserved, Read and written with
ones.
DMA Byte Count Register.
Contains the Two’s comple-
ment of the current size of the
remaining transmit or receive
buffer in bytes. This register is
incriminated by the Bus Inter-
face Unit. The DMABC register
is undefined until written.
Read/write
when STOP or SPND bits are
set.
Description
Description
accessible
accessible
accessible
only
only
only
Am79C961A
CSR88-89: Chip ID
Bit
31-28
27-12
11-1
0
CSR92: Ring Length Conversion
Bit
15-0
CSR94: Transmit Time Domain Reflectometry
Bit
15-10
9-0
XMTTDR
RCON
Name
Name
Name
RES
Count
Version. This 4-bit pattern is
silicon revision dependent.
Part Number. The 16-bit code
for the PCnet-ISA II controller is
0010001001100001b (2261h).
Manufacturer ID. The 11-bit
manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
Always a logic 1.
This register is exactly the same
as the Chip ID register in the
JTAG description.
This register is readable only
when STOP or SPND bits are
set.
Ring Length Conversion Regis-
ter. This register performs a
ring length conversion from an
encoded value as found in the
initialization block to a Two’s
complement value used for
bits 15–12 with an encoded
ring length, a Two’s comple-
mented value is read. The
RCON register is undefined
Read/write
when STOP or SPND bits are
set.
Reserved locations. Read and
written as zero.
Time
reflects the state of an internal
counter that counts from the
start of transmission to the
occurrence of loss of carrier.
TDR is incriminated at a rate of
10 MHz.
Read accessible only when
STOP or SPND bits are set.
Write operations are ignored.
XMTTDR is cleared by RESET.
internal counting. By writing
until written.
Domain
Description
Description
Description
accessible
Reflectometry
only
111