AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 66

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

descriptor rings. By default, a maximum of 128 ring
entries is permitted when utilizing the initialization
block, which uses values of TLEN and RLEN to specify
the transmit and receive descriptor ring lengths. How-
ever, the ring lengths can be manually defined (up to
65535) by writing the transmit and receive ring length
registers (CSR76,78) directly.
Each ring entry contains the following information:
Receive descriptor entries are similar (but not identical)
to transmit descriptor entries. Both are composed of
four registers, each 16 bits wide for a total of 8 bytes.
To permit the queuing and de-queuing of message
buffers, ownership of each buffer is allocated to either
the PCnet-ISA II controller or the host. The OWN bit
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The address of the actual message data buffer in
user or host memory
The length of the message buffer
Status information indicating the condition of the
buffer
Am79C961A
within the descriptor status information, either TMD or
RMD (see section on TMD or RMD), is used for this
purpose. “Deadly Embrace” conditions are avoided by
the ownership mechanism. Only the owner is permitted
to relinquish ownership or to write to any field in the
descriptor entry. A device that is not the current owner
of a descriptor entry cannot assume ownership or
change any field in the entry.
Descriptor Ring Access Mechanism
At initialization, the PCnet-ISA II controller reads the
base address of both the transmit and receive descrip-
tor rings into CSRs for use by the PCnet-ISA II control-
ler during subsequent operation.
When transmit and receive functions begin, the base
address of each ring is loaded into the current descrip-
tor address registers and the address of the next
descriptor entry in the transmit and receive rings is
computed and loaded into the next descriptor address
registers.