AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 61

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

SR_16B
SRSZ[3:0]
Vendor Defined Byte (PnP 0xF0)
LGCY_EN
0
1
1
1
1
0
0
0
0
1
1
1
1
SRAM[2:0]
SRSZ[3:0]
x
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
x
0
1
0
1
0
1
0
1
Legacy mode enable. When written
Shared Memory architecture mode.
The SRAM[2:0] bits are used for per-
forming address decoding on the
SA[15:13] address bits as shown in
the table below. S RAM[4] an d
SRAM[3] must reflect the external
address match logic for SA[17] and
SA[16], respectively. The SRAM[4:0]
bits are ignored when in the Bus
Master mode or in the Programmed
I/O Architecture mode.
Static RAM 16-bit access (PnP
0x4A). If asserted, the PCnet-ISA II
will respond to SRAM cycles as a
16-bit device. This bit should be set
if external logic is designed to assert
t h e M E M C S 1 6 s i g n a l w h e n
accesses to the shared memory are
decoded. This bit is ignored when in
the Bus Master mode or in the Pro-
grammed I/O Architecture mode.
Static RAM size (PnP 0x4B-0x4C).
Selects the size of the static RAM.
The SRSZ[3:0] bits are ignored
when in the Bus Master mode or in
the Programmed I/O Architecture
mode.
with a one, the PCnet-ISA II will not
respond to the Plug and Play initia-
tion key sequence (6A) but will
respond to the AMD key sequence
(6B). Therefore, it cannot be recon-
figured by the Plug and Play soft-
ware. When set to zero (default), the
x
1
0
0
0
0
0
0
0
1
1
1
1
SA[15:13]
0
0
1
1
0
0
1
1
No Static RAM Selected
Shared Memory Size
0
1
0
1
0
1
0
1
16 K
32 K
64 K
8 K
SRAM Size
(K bytes)
8, 16, 32, 64
8
8, 16
8
8, 16, 32
8
8, 16
8
Am79C961A
DXCVRP
IO_MODE
AEN_CS
APROM_EN
PCnet-ISA II will respond to the 6A
key sequence if the EEPROM read
was successful, otherwise it will re-
spond to the 6B key sequence.
DXCVR Polarity. The DXCVRP bit
sets the polarity of the DXCVR pin.
When DXCVRP is cleared (default),
the DXCVR pin is driven HIGH when
the Twisted Pair port is active or
SLEEP mode has been entered and
driven LOW when the AUI port is
active. When DXCVRP is set, the
DXCVR pin is driven LOW when the
Twisted Pair port is active or SLEEP
mode has been entered and driven
HIGH when the AUI port is active.
The DXCVRP should generally be
left cleared when the PCnet-ISA II is
being used with an external DC-DC
conver ter that has an active low
enable pin. The DXCVRP should
generally be set when the PC-
net-ISA II is being used with an ex-
ternal DC-DC converter that has an
active high enable pin.
I/O Mode. When set to one, the
internal selection will respond as a
16-bit port, (i.e. drive IOCS16 pin).
When IO_MODE is set to zero,
(Default), the internal I/O selection
will respond as an 8-bit port.
External Decode Logic for I/O Reg-
isters. When written with a one, the
PCnet-ISA II will use the AEN pin as
I/O chip select bar, to allow for exter-
nal decode logic for the upper ad-
dress bit of SA [9:5]. The purpose of
this pin is to allow I/O locations, not
suppor ted with the IOAM[3:0],
selection, to be defined outside the
range 0x200–0x3F7. When set to a
zero, (Default), I/O Selection will use
IOAM[3:0].
External Parallel IEEE Address
PROM. When set, the IRQ15 pin is
reconfigured to be an Address Chip
Select low, similar to APCS pin in the
existing PCnet-ISA (Am79C960)
device. The purpose of this bit is to
allow for both a serial EEPROM and
parallel PROM to coexist. When
A P R O M _ E N i s s e t , t h e I E E E
address located in the serial EE-
PROM will be ignored and parallel
access will occur over the PRDB
61