AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 84

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

During an odd byte read the swap buffer copies the
data from SD0-7 to the high byte. During an odd byte
write the Current Master swap buffer copies the data
from the high byte to SD0-7. The PCnet-ISA II control-
ler can be configured to be an 8-bit I/O resource even
in a 16-bit system; this is set by the EEPROM. It is rec-
ommended that the PCnet-ISA II controller be config-
ured for 8-bit only I/O bus cycles for maximum
compatibility with PC/AT clone motherboards.
When the PCnet-ISA II controller is in an 8-bit system
such as a PC/XT, SBHE and IOCS16 must be left
unconnected (these signals do not exist in the PC/XT).
This will force ALL resources (I/O and memory) to sup-
port only 8-bit bus cycles. The PCnet-ISA II controller
will function in an 8-bit system only if configured for Bus
Slave Mode.
Accesses to 16-bit resources (which do retur n
MEMCS16 or IOCS16) use either or both SD0–7 and
SD8–15. A word access is indicated by A0=0 and
SBHE=0 and data is transferred on all 16 data lines. An
even byte access is indicated by A0=0 and SBHE=1
and data is transferred on SD0–7. An odd-byte access
is indicated by A0=1 and SBHE=0 and data is trans-
ferred on SD8-15. It is illegal to have A0=1 and
SBHE=1 in any bus cycle. The PCnet-ISA II controller
returns only IOCS16; MEMCS16 must be generated by
external hardware if desired. The use of MEMCS16
applies only to Shared Memory Mode.
The following table describes all possible types of ISA
bus accesses, including Permanent Master as Current
Master and PCnet-ISA II controller as Current Master.
The PCnet-ISA II controller will not work with 8-bit
Address PROM Cycles External PROM
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA II controller Private Data
84
R/W
WR
WR
WR
WR
WR
RD
RD
RD
RD
RD
A0
0
1
0
1
0
0
1
0
1
0
SBHE
1
0
0
0
0
1
0
0
0
0
CS16
x
1
1
0
0
x
1
1
0
0
ISA Bus Accesses
Am79C961A
Master
Master
Master
Master
Slave
Slave
Slave
Slave
D0–7
Float
Float
memory while it is Current Master. Any descriptions of
8-bit memory accesses are for when the Permanent
Master is Current Master.
The two byte columns (D0–7 and D8–15) indicate
whether the bus master or slave is driving the byte.
CS16 is a shorthand for MEMCS16 and IOCS16.
Bus Master Mode
The PCnet-ISA II controller can be configured as a Bus
Master only in systems that support bus mastering. In
addition, the system is assumed to support 16-bit
memory (DMA) cycles (the PCnet-ISA II controller
does not use the MEMCS16 signal on the ISA bus).
This does not preclude the PCnet-ISA II controller from
doing 8-bit I/O transfers. The PCnet-ISA II controller
will not function as a bus master in 8-bit platforms such
as the PC/XT.
Refresh Cycles
Although the PCnet-ISA II controller is neither an origi-
nator or a receiver of refresh cycles, it does need to
avoid unintentional activity during a refresh cycle in bus
master mode. A refresh cycle is performed as follows:
First, the REF signal goes active. Then a valid refresh
address is placed on the address bus. MEMR goes ac-
tive, the refresh is performed, and MEMR goes inac-
tive. The refresh address is held for a short time and
them goes invalid. Finally, REF goes inactive. During
a refresh cycle, as indicated by REF being active, the
PCnet-ISA II controller ignores DACK if it goes active
until it goes inactive. It is necessary to ignore DACK
during a refresh because some motherboards gener-
ate a false DACK at that time.
Bus. The PCnet-ISA II controller will support only 8-bit
ISA I/O bus cycles for the address PROM; this limita-
tion is transparent to software and does not preclude
16-bit software I/O accesses. An access cycle begins
Master
Master
Master
D8–15
Slave
Slave
Float
Float
Float
Float
Float
Comments
Low byte RD
High byte RD with swap
16-Bit RD converted to low byte RD
High byte RD
16-Bit RD
Low byte WR
High byte WR with swap
16-Bit WR converted to
low byte WR
High byte WR
16-Bit WR