AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 86

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

within 60 ns of DACK going active. The Permanent
Master drives AEN inactive within 71 ns of MASTER
going active.
Access Phase
The ISA bus requires a wait of at least 125 ns after
MASTER is asserted before the new master is allowed
to drive the address, command, and data lines. The
PCnet-ISA II controller will actually wait 3 clock cycles
or 150 ns.
The following signals are not driven by the Permanent
Master and are simply pulled HIGH: BALE, IOCHRDY,
IOCS16, MEMCS16, SRDY. Therefore, the PCnet-ISA
II controller assumes the memory which it is accessing
is 16 bits wide and can complete an access in the time
programmed for the PCnet-ISA II controller MEMR and
MEMW signals. Refer to the ISA Bus Configuration
Register description section.
Release Phase
When the PCnet-ISA II controller is finished with the
bus, it drives the command lines inactive. 50 ns later,
the controller tri-states the command, address, and
data lines and drives DRQ inactive. 50 ns later, the con-
troller drives MASTER inactive.
The Permanent Master drives AEN active within 71 ns
of MASTER going inactive. The Permanent Master is
allowed to drive the command lines no sooner than 60
ns after DACK goes inactive.
Master Mode Memory Read Cycle
After the PCnet-ISA II controller has acquired the ISA
bus, it can perform a memory read cycle. All timing is
generated relative to the 20 MHz clock (network clock).
Since there is no way to tell if memory is 8-bit or 16-bit
or when it is ready, the PCnet-ISA II controller by
default assumes 16-bit, 1 wait state memory. The wait
state assumption is based on the default value in the
MSRDA register in ISACSR0.
The cycle begins with SA0-19, SBHE, and LA17-23
being presented. The ISA bus requires them to be valid
for at least 28 ns before a read command and the PC-
net-ISA II controller provides one clock or 50 ns of
setup time before asserting MEMR.
The ISA bus requires MEMR to be active for at least
219 ns, and the PCnet-ISA II controller provides a
default of 5 clocks, or 250 ns, but this can be tuned for
faster systems with the Master Mode Read Active
(MSRDA) register (see section 2.5.2). Also, if
IOCHRDY is driven LOW, the PCnet-ISA II controller
will wait. The wait state counter must expire and
IOCHRDY must be HIGH for the PCnet-ISA II controller
to continue.
The PCnet-ISA II controller then accepts the memory
read data. The ISA bus requires all command lines to
remain inactive for at least 97 ns before starting
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Am79C961A
another bus cycle and the PCnet-ISA II controller pro-
vides at least two clocks or 100 ns of inactive time.
The ISA bus requires read data to be valid no more
than 173 ns after receiving MEMR active and the PC-
net-ISA II controller requires 10 ns of data setup time.
The ISA bus requires read data to provide at least 0 ns
of hold time and to be removed from the bus within 30
ns after MEMR goes inactive. The PCnet-ISA II control-
ler requires 0 ns of data hold time.
Master Mode Memory Write Cycle
After the PCnet-ISA II controller has acquired the ISA
bus, it can perform a memory write cycle. All timing is
generated relative to a 20 MHz clock which happens to
be the same as the network clock. Since there is no
way to tell if memory is 8- or 16-bit or when it is ready,
the PCnet-ISA II controller by default assumes 16-bit, 1
wait state memory. The wait state assumption is based
on the default value in the MSWRA register in
ISACSR1.
The cycle begins with SA0-19, SBHE, and LA17-23
being presented. The ISA bus requires them to be valid
at least 28 ns before MEMW goes active and data to be
valid at least 22 ns before MEMW goes active. The PC-
net-ISA II controller provides one clock or 50 ns of
setup time for all these signals.
The ISA bus requires MEMW to be active for at least
219 ns, and the PCnet-ISA II controller provides a
default of 5 clocks, or 250 ns, but this can be tuned for
faster systems with the Master Mode Write Active
(MSWRA) register (ISACSR1). Also, if IOCHRDY is
driven LOW, the PCnet-ISA II controller will wait.
IOCHRDY must be HIGH for the PCnet-ISA II controller
to continue.
The ISA bus requires data to be valid for at least 25 ns
after MEMW goes inactive, and the PCnet-ISA II con-
troller provides one clock or 50 ns.
The ISA bus requires all command lines to remain
inactive for at least 97 ns before starting another bus
cycle. The PCnet-ISA II controller provides at least two
clocks or 100 ns of inactive time when bit 4 in ISACSR2
is set. The EISA bus requires all command lines to
remain inactive for at least 170 ns before starting
another bus cycle. When bit 4 in ISACSR4 is cleared,
the PCnet-ISA II controller provides 200 ns of inactive
time.
Back-to-Back DMA Requests
The PCnet-ISA II provides for fair bus bandwidth shar-
ing between two bus mastering devices on the ISA bus
through an adaptive delay which is inserted between
back-to-back DMA requests.
When the PCnet-ISA II requires bus access immedi-
ately following a bus ownership period, it first checks
the status of the three currently unused DRQ pins. If a