AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet
AM79C961AVIW
Specifications of AM79C961AVIW
Related parts for AM79C961AVIW
AM79C961AVIW Summary of contents
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Am79C961A ™ PCnet -ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA DISTINCTIVE CHARACTERISTICS Single-chip Ethernet controller for the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) buses Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards Supports full ...
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GENERAL DESCRIPTION The PCnet-ISA II controller, a single-chip Ethernet con- troller highly integrated system solution for the PC-AT Industry Standard Architecture (ISA) architec- ture designed to provide flexibility and compatibil- ity with any existing PC application. ...
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BLOCK DIAGRAM: BUS MASTER MODE AEN DACK[3, 5–7] DRQ[3, 5–7] IOCHRDY IOCS16 IOR ISA Bus IOW Interface Unit IRQ[ 10, 11, 12] MASTER MEMR MEMW REF RESET SBHE BALE SD[0-15] Buffer LA[17-23] Management SA[0-19] Unit SLEEP SHFBUSY ...
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TABLE OF CONTENTS Am79C961A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AVSS1– ...
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Vendor Defined Byte (PnP 0xF0 ...
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Instruction Register and Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CSR32-33: Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 ...
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RMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Layout Recommendations for Reducing Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 DECOUPLING LOW-PASS R/C FILTER DESIGN . . ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C961A K DEVICE NUMBER/DESCRIPTION Am79C961A PCnet-ISA II Jumperless Single-Chip Ethernet Controller for ISA Valid ...
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CONNECTION DIAGRAMS: BUS MASTER MODE DVSS3 1 MASTER 2 DRQ7 3 DRQ6 4 DRQ5 5 DVSS10 6 DACK7 7 DACK6 8 DACK5 9 LA17 10 LA18 11 LA19 12 LA20 13 DVSS4 14 LA21 15 LA22 16 LA23 17 SBHE ...
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PIN DESIGNATIONS: BUS MASTER MODE Listed by Pin Number Pin No. Pin Name Pin No. 1 DVSS3 34 2 MASTER 35 3 DRQ7 36 4 DRQ6 37 5 DRQ5 38 6 DVSS10 39 7 DACK7 40 8 DACK6 41 9 ...
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PIN DESIGNATIONS: BUS MASTER MODE Listed by Pin Name Pin Name Pin No. Pin Name AEN 44 DVSS12 AVDD1 103 DVSS13 AVDD2 108 DVSS2 AVDD3 96 DVSS3 AVDD4 91 DVSS4 AVSS1 100 DVSS5 AVSS2 98 DVSS6 BALE 55 DVSS7 BPCS ...
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PIN DESIGNATIONS: BUS MASTER MODE Listed by Group Pin Name ISA Bus Interface AEN Address Enable BALE Bus Address Latch Enable DACK[3, 5–7] DMA Acknowledge DRQ[3, 5–7] DMA Request IOCHRDY I/O Channel Ready IOCS16 I/O Chip Select 16 IOR I/O ...
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PIN DESIGNATIONS: BUS MASTER MODE (continued) Listed by Group Pin Name Attachment Unit Interface (AUI Twisted Pair Transceiver Interface (10BASE-T) RXD TXD TXPD IEEE 1149.1 Test Access Port Interface (JTAG) TCK TDI TDO TMS Power Supplies AVDD ...
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PIN DESCRIPTION: BUS MASTER MODE These pins are part of the bus master mode. In order to understand the pin descriptions, definition of some terms from a draft of IEEE P996 are included. IEEE P996 Terminology Alternate Master: Any device ...
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IRQ 10, 11, 12, 15 Interrupt Request Output An attention signal which indicates that one or more of the following status flags is set: BABL, MISS, MERR, RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT. All status ...
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Likewise, the data on SD0-15 is latched by the PCnet-ISA II controller when performing bus master reads and slave write operations. Board Interface IRQ12/FlashWE Flash Write Enable Output Optional interface ...
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SHFBUSY Shift Busy Input/Output This pin indicates that a read from the external EEPROM is in progress active only when data is being shifted out of the EEPROM due to a hardware RESET or assertion of the EE_LOAD ...
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CONNECTION DIAGRAMS: BUS SLAVE MODE DVSS3 1 SMA 2 SA0 3 SA1 4 SA2 5 DVSS10 6 SA3 7 SA4 8 SA5 9 SA6 10 SA7 11 SA8 12 SA9 13 DVSS4 14 SA10 15 SA11 16 SA12 17 SBHE ...
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BLOCK DIAGRAM: BUS SLAVE MODE AEN IOCHRDY IOR IOW ISA Bus IRQ[ Interface 10, 11, 12] Unit IOCS16 MEMR MEMW REF RESET SA[0-15] SBHE SD[0-15] Buffer Management Unit SMA SLEEP BPAM SMAM SHFBUSY EEPROM EEDO Interface EEDI ...
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PIN DESIGNATIONS: BUS SLAVE MODE Listed by Pin Number Pin # Name 1 DVSS3 2 SMA 3 SA0 4 SA1 5 SA2 6 DVSS10 7 SA3 8 SA4 9 SA5 10 SA6 11 SA7 12 SA8 13 SA9 14 DVSS4 ...
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PIN DESIGNATIONS: BUS SLAVE MODE Listed by Pin Name Name Pin# AEN 44 AVDD1 103 AVDD2 108 AVDD3 96 AVDD4 91 AVSS1 100 AVSS2 98 BPAM 55 BPCS 126 CI- 106 CI+ 107 DI- 104 DI+ 105 DO- 101 DO+ ...
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PIN DESIGNATIONS: BUS SLAVE MODE Listed by Group Pin Name Pin Function ISA Bus Interface AEN Address Enable IOCHRDY I/O Channel Ready IOCS16 I/O Chip Select 16 IOR I/O Read Select IOW I/O Write Select IRQ[ 10, ...
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PIN DESIGNATIONS: BUS SLAVE MODE Listed by Group Pin Name Attachment Unit Interface (AUI Twisted Pair Transceiver Interface (10BASE-T) RXD TXD TXPD IEEE 1149.1 Test Access Port Interface (JTAG) TCK TDI TDO TMS Power Supplies AVDD AVSS ...
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PIN DESCRIPTION: BUS SLAVE MODE ISA Interface AEN Address Enable Input This signal must be driven LOW when the bus performs an I/O access to the device. IOCHRDY I/O Channel Ready Output When the PCnet-ISA II controller is being accessed, ...
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SBHE System Bus High Enable Input This signal indicates the HIGH byte of the system data bus used. There is a weak pull-up resistor on this pin. If the PCnet-ISA II controller is installed in an 8-bit ...
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PRDB1/EEDI Private Data Bus Bit 1/Data In Input/Output A multifunction pin which serves as PRDB1 of the private data bus and, when ISACSR3 bit 4 is set, changes to become DATA In to the EEPROM. PRDB0/EESK Private Data Bus Bit ...
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PIN DESCRIPTION: NETWORK INTERFACES AUI CI+, CI– Control Input This is a differential input pair used to detect Collision (Signal Quality Error Signal). DI+, DI– Data In This is a differential receive data input pair to the PC- net-ISA II ...
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CONNECTION DIAGRAM TQFP ...
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PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144) Listed by Pin Number Pin No. Pin Name Pin No DVSS3 38 3 MASTER 39 4 DRQ7 40 5 DRQ6 41 6 DRQ5 42 7 DVSS10 43 8 DACK7 ...
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PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144) Listed by Pin Name Pin Name Pin No. Pin Name AEN 48 DVSS3 AVDD1 113 DVSS4 AVDD2 118 DVSS5 AVDD3 103 DVSS6 AVDD4 98 DVSS7 AVSS1 110 DVSS8 AVSS2 105 DVSS9 BALE 59 ...
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PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) Listed by Pin Number Pin No. Pin Name Pin No DVSS3 38 3 SMA 39 4 SA0 40 5 SA1 41 6 SA2 42 7 ...
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PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) Listed by Pin Name Pin Name Pin No. Pin Name AEN 48 EECS AVDD1 113 IOCHRDY AVDD2 118 IOCS16 AVDD3 103 IOR AVDD4 98 IOW AVSS1 110 IRQ10 AVSS2 ...
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BLOCK DIAGRAM: PCMCIA MODE REG CE2 CE1 WAIT INPACK STSCHG PCMCIA Bus IORD Interface IOWR IREQ IOIS16 RESET A[0-15] D[0-15] PCMCIA_MODE Management SMA SLEEP SMAM SHFBUSY EEPROM EEDO Optional Interface EEDI EESK EECS DVDD[1-7] DVSS[1-13] AVDD[1-4] ...
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PIN DESIGNATIONS: PCMCIA MODE (TQFP 144) Listed by Pin Number Pin No. Pin Name Pin No DVSS3 38 3 SMA 39 4 SA0 40 5 SA1 41 6 SA2 42 7 DVSS10 43 8 SA3 44 ...
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PIN DESIGNATIONS: PCMCIA MODE (TQFP 144) Listed by Pin Name Pin Name Pin No. Pin Name AVDD1 113 INPACK AVDD2 118 IOIS16 AVDD3 103 IORD AVDD4 98 IOWR AVSS1 110 IREQ AVSS2 105 LED0 CE1 59 LED1 CE2 19 LED2 ...
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PIN DESCRIPTION: PCMCIA MODE The PCMCIA pins function as described in the PCMCIA Specification Revision 2.1. Please refer to it for more details. The non-PCMCIA pins used by the 144-pin TQFP package have the same functions as described by “Pin ...
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PCMCIA vs. ISA Pinout Comparison The pins listed below are pin definition changes spe- cific to PCMCIA mode: In PCMCIA mode, a number of the input pins have internal resistors turned on with a Pin Number TQFP144 ...
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PCMCIA MODE BLOCK DIAGRAM SA[0–15] System Address Bus PCMCIA Bus PCMCIA Control SD[0–15] 16-Bit System Data (Upper Address pin) Note: SMAM shown only for Shared Memory architecture designs. SMAM should be tied HIGH on the PCnet-ISA II for Programmed I/O ...
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FUNCTIONAL DESCRIPTION PCMCIA Operation When a PCMCIA card is first plugged into a PCMCIA host, all PCMCIA cards respond as a memory only device. In the PCMCIA standard there are two memory spaces, common memory and attribute memory. The REG ...
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FLASH MEMORY MAP AND CARD REGISTERS Common Memory Attribute Memory 44 FLASH Common Memory Reserved CCR 3 CCR 2 CCR 1 CCR 0 (Not Available) CIS Data (Unused) Am79C961A 131070 Byte (1FFFEh) 1024 Byte (400h) 1022 Byte (3FEh) 1016 Byte ...
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FUNCTIONAL DESCRIPTION The PCnet-ISA II controller is a highly integrated system solution for the PC-AT ISA architecture. It provides a Full Duplex Ethernet controller, AUI port, and 10BASE-T transceiver. The PCnet-ISA II controller can be directly in- terfaced to an ...
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System Data SD[0-15] PCnet-ISA II ISA Bus 24-Bit System Address SA[0-19] LA[17-23] Bus Master Block Diagram Plug and Play Compatible SD[0-15] 16-Bit PCnet-ISA II System Controller Data SA[0-19] LA[17-23] 24-Bit System IRQ15/APCS IRQ12/FlashWE Address ISA Bus Bus Master Block ...
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Bus Slave Mode System Interface The Bus Slave mode is the other fundamental operat- ing mode available on the PCnet-ISA II controller. Within the Bus Slave mode, the PCnet-ISA II can be programmed for a Shared Memory or Programmed I/O ...
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System Data SD[0] PCnet-ISA II Controller 24-Bit System Address SA[0] SHFBUSY ISA Bus V CC Note: SMAM shown only for Shared Memory architecture designs. SMAM should be tied HIGH on the PCnet-ISA II for Programmed I/O architecture designs. Plug ...
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PLUG AND PLAY Plug and Play is a standardized method of configuring jumperless adapter cards in a system. Plug and Play is a Microsoft standard and is based on a central software configuration program, either in the operating system or ...
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This pattern must be sequential, i.e., any other I/O access to this I/O port will reset the state machine which is checking the pattern. Interrupts should be disabled during this time to eliminate any extraneous I/O cycles. The ...
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If a card was driving the bus or if the card was in high impedance and did not sense another card driving the bus, then it should prepare for the next pair of I/O reads. The card shifts the serial ...
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State Active Commands Reset Wait for Key Isolation Set RD_DATA Port Serial Isolation Wake[CSN] Notes: 1. CSN = Card Select Number. 2. RESET_DRV causes a state transition from the current state to Wait for Key and sets all CSNs to ...
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Address Name Port Value Set RD_DATA Port 0x00 Serial Isolation 0x01 Config Control 0x02 Wake[CSN] 0x03 Resource Data 0x04 Status 0x05 Card Select Number 0x06 Logical Device Number 0x07 Plug and Play Standard Registers Definition Writing to this location modifies ...
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PLUG AND PLAY LOGICAL DEVICE CONFIGURATION REGISTERS The PCnet-ISA II controller supports a subset of the defined Plug and Play logical device control registers. The reason for only supporting a subset of the registers is that the PCnet-ISA II controller ...
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Register Name Index Interrupt request level 0x70 select 0 Interrupt request type 0x71 select 0 Register Name Index DMA channel select 0 0x74 DMA channel select 1 0x75 DETAILED FUNCTIONS EEPROM Interface The EEPROM supported by the PCnet-ISA II controller ...
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Basic EEPROM Byte Map The following is a byte map of the XXC56 series of EEPROMs used by the PCnet-ISA II Ether net IEEE Address (0h) (Bytes 0 – 5) (8h) EISA Config Reg. (Ah) Internal Registers (11h) Plug and ...
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AMD Device Driver Compatible EEPROM Byte Map The following is a byte map of the XXC56 series of EEPROMs used by the PCnet-ISA II Ethernet Controller. This byte map is for the case where a Word Location ...
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Plug and Play Register Map The following chart and its bit descriptions show the internal configuration registers associated with the Plug and Play Register Bit 7 Bit 6 0x00 0x01 0x02 0 0 0x03 0x04 0x05 0 0 0x06 0x07 ...
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The following chart and its bit descriptions show the internal command registers associated with the Plug Plug and Bit 7 Bit 6 Play Register 0x60 0 0 0x61 IOAM2 IOAM1 0x70 0 0 0x71 0 0 0x74 0 0 0x40 ...
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Plug & Play Register Locations Detailed Description (Refer to the Plug & Play Register Map above) IOAM[3:0] I/O Address Match to bits [8: bus (PnP 0x60–0x61). Controls the base address of PCnet-ISA II. The IOAM will be written ...
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Shared Memory architecture mode. The SRAM[2:0] bits are used for per- forming address decoding on the SA[15:13] address bits as shown in the table below. S RAM[ SRAM[3] must reflect the external address match logic for SA[17] and ...
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When APROM_EN is cleared, default state, the IEEE address will be read in from the serial device and written to an internal RAM. When the I/O space of the IEEE PROM is selected, PCnet-ISA II, will access the contents ...
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Interface To use a Flash-type device with the PCnet-ISA II controller, Flash Select is set in register 0F0h of the Plug and Play registers. Flash Select is cleared by RESET (default). In bus master mode, BPCS becomes Flash_OE and IRQ12 ...
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If the TIMER bit is set, the cycles required in a descriptor access may be performed as ...
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The general rule is that the longer the Bus Grant latency or the slower the bus transfer operations ...
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By default, a maximum of 128 ring entries is permitted when utilizing the initialization block, which uses values of TLEN and RLEN to specify the transmit and receive descriptor ring lengths. How- ever, the ring lengths can be ...
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Base Address Pointer to Initialization Block CSR2 IADR[23:16] RES Initialization Block MODE PADR[15:0] PADR[31:16] PADRF[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN RES RDRA[23:16] TDRA[15:0] TLEN RES TDRA[23:16] Polling When there is no channel activity and there is no pre- ...
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All information collected during polling activity will be stored internally in the appropriate CSRs. (i.e. CSR18–19, CSR40, CSR20–21, CSR42, CSR50, CSR52). Unowned descriptor status will be internally ignored. A typical receive poll occurs under the following conditions: 1. ...
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TDTE with the BUFF and UFLO bits being set. If DXSUFLO is 0 (bit 6 CSR3), then this will cause the transmitter to be dis- abled (CSR0, TXON = 0). The PCnet-ISA II ...
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RDTE shows valid ownership, then it proceeds to a poll of the next RDTE. Following this poll, and regardless of the outcome of this poll, transfers of receive data from the FIFO may begin. ...
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The receive section of the MAC engine will detect an incoming preamble sequence and lock to the encoded clock. The internal MENDEC will decode the serial bit stream and present ...
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The MAC engine will wait for the network to go inactive before attempting to receive the next packet. Media Access Management The basic requirement for all stations on the ...
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However, since IPG shrinkage below 4 s will rarely be encountered on a correctly configured network, and since the fragment size will be larger than the 4 s blinding window, then the IPG counter will be ...
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External Crystal Characteristics Parameter Min 1. Parallel Resonant Frequency 2. Resonant Frequency Error –50 ( pF) 3.Change in Resonant Frequency With Respect –40 To Temperature (0 – pF)* 4. Crystal Capacitance 5. Motional ...
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External Clock Drive Characteristics When driving the oscillator from an external clock source, XTAL2 must be left floating (unconnected). An external clock having the following characteristics must be used to ensure less than 0.5 ns jitter Clock ...
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PLL Tracking After clock acquisition, the phase-locked clock is com- pared to the incoming transition at the bit cell center (BCC) and the resulting phase error is applied to a cor ...
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LOW-to-HIGH transition Jitter Tolerance Definition The MENDEC utilizes a clock capture circuit to align its internal data strobe with an incoming bit stream. The clock acquisition circuitry requires ...
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When the link test function is enabled (DLNKTST bit in CSR15 is cleared), the absence of link beat pulses and receive data on the RXD pair will cause the TMAU to go into the Link Fail state. In the Link ...
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COL stays active for 2 bit times at the end of a collision. Signal Quality Error (SQE) Test (Heartbeat) Function The SQE function is disabled when the 10BASE-T port is selected and in ...
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EADI (External Address Detection Interface) This interface is provided to allow external address fil- tering selected by setting the EADISEL bit in ISACSR2. This feature is typically utilized for terminal servers, bridges and/or router type products. The use ...
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MENDEC logic. The LA (unlatched address) pins are removed and become the GPSI signals, therefore, only 20 bits of address space is available. The table below shows the GPSI pin configuration: To invoke the GPSI signals, follow the procedure below: ...
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IEEE 1149.1 Test Access Port Interface An IEEE 1149.1 compatible boundary scan Test Access Port is provided for board-level continuity test and diag- nostics. All digital input, output, and input/output pins are tested. Analog pins, including the AUI differential driver ...
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This LED0 pin can be used to drive a LED and/or external hardware that directly controls the SLEEP pin of the PCnet-ISA II controller. This configuration effectively wakes the system when ...
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During an odd byte read the swap buffer copies the data from SD0-7 to the high byte. During an odd byte write the Current Master swap buffer copies the data from the high byte to SD0-7. The PCnet-ISA II control- ...
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Permanent Master driving AEN LOW, driving the addressess valid, and driving IOR active. The PCnet-ISA II controller detects this combination of sig- nals and arbitrates for the Private Data Bus (PRDB) if necessary. IOCHRDY is driven LOW during ...
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DACK going active. The Permanent Master drives AEN inactive within MASTER going active. Access Phase The ISA bus requires a wait of at least 125 ns after MASTER is asserted before the new ...
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DRQ pin than the one currently being used by the PCnet-ISA II is asserted, the PCnet-ISA II will wait 2.6 s after the deassertion of DACK before re-asserting its DRQ pin lower priority DRQ pin is ...
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ISA Configuration Register Cycles The ISA configuration register is accessed by placing the address of the desired register into the RAP and reading the IDP. The ISACSR bus cycles are identical to all other PCnet-ISA II controller register bus cycles. ...
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The only way to configure the PCnet-ISA II controller for 8-bit ISA bus cycles for SRAM accesses is to con- figure the entire PCnet-ISA II controller to support only 8-bit ISA bus cycles. This is accomplished by leaving the SBHE ...
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SRAM to be performed without intervening writes to the SRAM Address Pointer. Since buffer accesses comprise a high percentage of all accesses to the SRAM, and buffer accesses are typically performed ...
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The PCnet-ISA II controller will append pad bytes dependent on the actual number of bits transmitted onto the network. Once the last data byte of the frame has completed prior to appending the FCS, the PCnet-ISA II ...
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Abnormal network conditions include: Loss of carrier Late collision SQE Test Error (Does not apply to 10BASE-T port.) These should not occur on a correctly configured 802.3 network, and will be reported if they do. When an error occurs in ...
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Bits Bits Preamble SYNCH 1010....1010 10101011 Start of Packet at Time= 0 Increasing Time IEEE/ANSI 802.3 Frame and Length Field Transmission Order Receive FCS Checking Reception and checking of the received FCS is per- formed automatically by the ...
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The PCnet-ISA II chip has two dedicated FCS genera- tors, eliminating the ...
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Refer to the section “ISA Bus Configuration Registers” for information on LED control via the ISACSRs. MAGIC PACKET OPERATION In the Magic Packet mode, PCnet-ISA II completes any transmit and receive operations in progress, suspends normal activity, and enters into ...
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PCNET-ISA II CONTROLLER REGISTERS The PCnet-ISA II controller implements all LANCE (Am7990) registers, plus a number of additional regis- ters. The PCnet-ISA II controller registers are compat- ible with the original LANCE, but there are some places where previously reserved ...
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MERR is set by the Bus Inter- face Unit and cleared by writing a “1". Writing a “0" has no effect. MERR is cleared by RESET or by setting the STOP bit. 10 RINT Receive Interrupt is set after re- ...
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TDMD is cleared by RESET or by setting the STOP bit. 2 STOP STOP assertion disables the chip from all external activity. The chip remains inactive until either STRT or INIT are set. If STOP, STRT and INIT are all ...
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When DXSUFLO is set to ZERO, the transmitter is turned off when an UFLO error occurs (CSR0, TXON = 0). When DXSUFLO is set to ONE, the PCnet-ISA gracefully recovers from an UFLO error. It scans the transmit descriptor ring ...
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Media Access section. Read/Write accessible. EMBA is cleared by RESET and is not affected by STOP. 2-0 RES Reserved locations. Written as zero and read as undefined. CSR4: Test and Features Control Bit Name ...
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MFCOM is set by Reset and is not affected by STOP. 7-6 RES Reserved locations. Read and written as zero. 5 RCVCCO Receive Collision Counter Over- flow. This bit indicates the Receive Collision Counter (CSR114) has overflowed. It can be ...
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Read/Write accessible always. SPND is cleared by asserting the RESET pin, reading the RESET register, or setting the STOP bit 1 MP_MODE Magic Packet Mode. Setting this bit is a prerequisite for entering the Magic Packet mode. It also redefines ...
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Read/write when STOP or SPND bits are set. CSR12: Physical Address Register, PADR[15:0] Bit Name Description 15-0 PADR[15:0] Physical Address PADR[15:0]. initialized either automatically by loading the initialization block or directly by an I/O write to this register. The PADR ...
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MENDECL MENDEC Loopback Mode. See the description of the LOOP bit in CSR15. Read/write when STOP or SPND bits are set. 9 LRT/TSEL Low Receive Threshold (T-MAU Mode only) Transmit Mode Select (AUI Mode only) LRT Low Receive Threshold. ...
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In loopback mode, this bit deter- mines if the transmitter appends FCS or if the receiver checks the FCS. This bit was called DTCR in the LANCE (Am7990). Read/write when STOP or SPND bits are set. 2 LOOP Loopback Enable ...
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CSR22-23: Next Receive Buffer Address Bit Name Description 31-24 RES Reserved locations. Written as zero and read as undefined. 23-0 NRBA Contains the next receive buffer address to which the PCnet-ISA II controller will store incoming frame data. Read/write when ...
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CRBC Current Receive Byte Count. This field is a copy of the BCNT field of RMD2 of the current receive descriptor. Read/write when STOP or SPND bits are set. CSR42-43: Current Transmit Status and Byte Count Bit Name Description ...
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Read/write accessible only when STOP or SPND bits are set. CSR52-53: Temporary Storage Bit Name Description 31-0 TMP2 Temporary Storage location. Read/write when STOP or SPND bits are set. CSR54-55: Temporary Storage Bit Name Description 31-0 TMP3 Temporary Storage location. ...
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CSR70-71: Temporary Storage Bit Name Description 31-0 TMP8 Temporary Storage location. Read/write when STOP or SPND bits are set. CSR72: Receive Ring Counter Bit Name Description 15-0 RCVRC Receive Ring Counter location. Contains a Two’s complement binary number used to ...
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RCVFW[1:0] Bytes Received 11-10XMTSP[1:0]Transmit Start Point. XMTSP controls the point at which preamble transmission attempts commence in relation to the number of bytes written to the transmit FIFO for the current transmit frame. When the ...
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The DMABAT register is unde- fined until written. When the Bus Activity Timer register (CSR82: DMABAT) is enabled, the PCnet-ISA II con- troller will relinquish the bus when either the time specified in DMABAT has elapsed or the number of ...
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CSR96-97: Bus Interface Scratch Register 0 Bit Name Description 31-0 SCR0 This register is shared between the Buffer Management Unit and the Bus Interface Unit. All Descriptor Data tions between the BIU and BMU are written and read through SCR0 ...
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This mode will reconfigure the External Address Pins so that the GPSI port is exposed. This allows bypassing the MENDEC- TMAU logic. This bit should only be set if the external logic sup- ports GPSI operation. Damage to the device ...
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ISA Bus Configuration Registers The ISA Bus Data Port (IDP) allows access to registers which are associated with the ISA bus. These registers are called ISA Bus Configuration Registers (ISACSRs), and are indexed by the value in the Register Address ...
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SRAMDP (ISACSR0). ISACSR2: Miscellaneous Configuration 1 Bit Name Description 15 MODE_STATUS Mode Status. This is a read-only register which indicates whether the PCnet-ISA II ...
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AUI port is active, the DXCVR is driven such that an external DC-DC converter disabled. The actual polarity of the DXCVR pin is determined by the DXCVRP bit in PnP Register 0xF0. ...
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EE_EN, for detailed use of this bit). 2 EECS EEPROM Chip Select. EECS asserts the chip select to the Serial EEPROM. (Refer to Bit 4 above, EE_EN, for detailed use of this bit Serial Shift Clock. SK controls ...
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RES Reserved locations. Read and written as zero. 5 RCVADDM Receive Address Match. This bit when set allows for LED control of only receive packets which match internal address match. 4 XMT E ...
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XMT E Enable Transmit Status Signal. Indicates PCnet-ISA II controller transmit activity. 0 disables the signal, 1 enables the signal. 3 RVPOL E Enable Receive Polarity Signal. Enables LED pin ...
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COL E Enable Collision Signal. Indi- cates collision activity on the network. 0 disables the signal, 1 enables the signal. ISACSR8: Software Configuration Register (Read-Only Register) Bit Description Read-only image of SRAM(3:0) of PnP register 15-12 0x48-0x49. Read-only image ...
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RDRA and TDRA TDRA and RDRA indicate where the transmit and receive descriptor rings, respectively, begin. Each DRE must be located on an 8-byte boundary. LADRF The Logical Address Filter (LADRF 64-bit mask that is used to accept ...
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Receive Descriptors The Receive Descriptor Ring Entries (RDREs) are composed of four receive message fields (RMD0-3). Together they contain the following information: The address of the actual message data buffer in user (host) memory The length of that message buffer ...
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PCnet-ISA II controller. 11-0 BCNT BUFFER BYTE COUNT is the length of the buffer pointed to by this descriptor, expressed as the two’s complement of the length of the buffer. This field is written by the host ...
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STP START OF PACKET indicates that this is the first buffer to be used by the PCnet-ISA II con- troller for this frame used for data chaining buffers. The STP bit must be set in the first ...
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If DRTY = 1 in the MODE register, RTRY will set after one failed transmission at- tempt. RTRY is written by the PCnet-ISA II controller. 09-00 TDR TIME DOMAIN REFLECTOME- TRY reflects the state of an inter- nal PCnet-ISA ...
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Register Summary Ethernet Controller Registers (Accessed via RDP Port) RAP Addr Symbol 00 CSR0 01 CSR1 02 CSR2 03 CSR3 04 CSR4 05 CSR5 06 CSR6 07 CSR7 08 CSR8 09 CSR9 10 CSR10 11 CSR11 12 CSR12 13 CSR13 ...
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Register Summary Ethernet Controller Registers (Accessed via RDP Port) RAP Addr Symbol 64-65 CSR64 66-67 CSR66 68-69 CSR68 70-71 CSR70 72 CSR72 74 CSR74 76 CSR76 78 CSR78 80 CSR80 82 CSR82 84-85 CSR84 86 CSR86 88-89 CSR88 92 CSR92 ...
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Register Summary ISACSR—ISA Bus Configuration Registers (Accessed via IDP Port) RAP Addr Mnemonic 0 MSRDA 1 MSWRA LED0 5 LED1 6 LED2 7 LED3 DUP * This value can be 0000H for ...
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SYSTEM APPLICATION ISA Bus Interface Compatibility Considerations Although 8 MHz is now widely accepted as the standard speed at which to run the ISA bus, many machines have been built which operate at higher speeds with non-stan- dard timing. Some ...
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System Data SD[0–15] PCnet-ISA II Controller ISA 24-Bit System Bus Address SA[0–19] LA[17–23] Bus Master Block Diagram Plug and Play Compatible SD[0–15] 16-Bit System Data PCnet-ISA II Controller SA[0] 24-Bit LA[17–23] System ISA Address IRQ15/ IRQ12/FlashWE Bus Bus Master ...
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SD[0–15] 16-Bit System Data SA[0–15] 24-Bit System Address SMAM SHFBUSY BPAM ISA Bus V CC Shared Memory Block Diagram Plug and Play Compatible PRAB(0:15) BPCS PRDB[0–7] PCnet-ISA II Controller PRDB[2]/EEDO PRDB[1]/EEDI PRDB[0]/EESK EECS SROE SRWE Am79C961A A[0–15] Boot PROM CE ...
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SD[0–15] 16-Bit System Data PCnet-ISA II Controller 24-Bit System Address SA[0–19] SHFBUSY ISA Bus V CC Shared Memory Block Diagram Plug and Play Compatible with Flash Memory Support Optional Address PROM Interface The suggested address PROM is the Am27LS19, a ...
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A13–A0 DQ7–DQ0 27C128 16K x 8 EPROM CE OE Static RAM Interface (for Shared Memory Only) The SRAM is an 8Kx8 or 32Kx8 device. The PCnet-ISA II controller can support 64 Kbytes of SRAM address space. The PCnet-ISA II controller ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . – +150 C Ambient Temperature . . . . . . . . . . . . . . . . ...
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DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description Attachment Unit Interface (continued) Transmit Differential Output Idle V AODOFF Voltage Transmit Differential Output Idle I AODOFF Current Transmit Output Common Mode V CMT Voltage DO Transmit Differential Output V ODI Voltage Imbalance ...
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DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description Twisted Pair Interface (continued) V RXD Switching Threshold RXDTH TXD and TXP Output HIGH V TXH Voltage TXD and TXP Output LOW V TXL Voltage TXD and TXP Differential Output V TXI Voltage ...
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SWITCHING CHARACTERISTICS: BUS MASTER MODE (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices) Parameter Symbol Parameter Description Input/Output Write Timing AEN, SBHE, SA0–9 Setup to t IOW1 IOW AEN, SBHE,SA0–9 Hold After t IOW2 ...
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SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued) Parameter Parameter Description Symbol Master Mode Bus Release t Command Deassert to MMBR1 t DRQ to DACK MMBR2 t DRQ to MASTER MMBR3 DRQ to Command, SBHE, t MMBR4 SA0–19, LA17–23 Tristated Master Write ...
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SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued) Parameter Symbol Parameter Description Master Mode Address PROM Read t IOR to APCS MA1 t APCS Active MA2 t PRDB Setup to APCS MA3 t PRDB Hold After APCS MA4 t APCS to IOCHRDY ...
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SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH READ CYCLE Parameter Parameter Description Symbol REF, SBHE,SA0–19 Setup to t MFR1 MEMR REF, SBHE,SA0–19 Hold from t MFR2 MEMR t IOCHRDY to MEMR MFR3 t MEMR Inactive MFR4 t MEMR to BPCS MFR5 t ...
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SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices) Parameter Parameter Description Symbol Input/Output Write Timing AEN, SBHE, SA0–9 Setup to t IOW1 IOW AEN, SBHE,SA0–9 Hold from t IOW2 ...
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SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued) Parameter Parameter Description Symbol Memory Read Timing SA0–15, SBHE, SMAM/BPAM t MR1 Setup to MEMR SA0–15, SBHE, SMAM/BPAM t MR2 Hold from MEMR t MEMR Inactive MR3 t SD Hold from MEMR MR4 t ...
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SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued) Parameter Symbol Parameter Description SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus (continued) PRDB Setup to PRAB Change, t PR8 APROM Access PRDB Hold After PRAB Change, t PR9 APROM Access ...
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SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH READ CYCLE Parameter Symbol Parameter Description BPAM, REF, SBHE, SA0–19 Setup t MFR1 to MEMR BPAM, REF, SBHE, SA0–19 Hold t MFR2 from MEMR t IOCHRDY to MEMR MFR3 t MEMR Inactive MFR4 t MEMR ...
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SWITCHING CHARACTERISTICS: EADI (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices) Parameter Symbol Parameter Description t SRD Setup to SRDCLK EAD1 t SRD Hold to SRDCLK EAD2 t SF/BD Change to EAD3 EAR Deassertion ...
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SWITCHING CHARACTERISTICS: GPSI (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices) Parameter Parameter Description Symbol Transmit Timing t STDCLK Period (802.3 Compliant) GPT1 t STDCLK HIGH Time GPT2 t TXDAT and TXEN Delay from ...
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SWITCHING CHARACTERISTICS: AUI (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices) Parameter Symbol Parameter Description AUI Port t DO+,DO- Rise Time (10% to 90%) DOTR t DO+,DO- Fall Time (90% to 10%) DOTF t ...
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SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices) Parameter Symbol Parameter Description Transmit Timing t Transmit Start of Idle TETD t Transmitter Rise Time TR t Transmitter Fall Time TF ...
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SWITCHING TEST CIRCUITS WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from May Will be Change Changing from from Don’t Care, ...
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SWITCHING TEST CIRCUITS Sense Point DO+ DO– 150 Normal and Three-State Outputs AV DD 52.3 Test Point 154 100 AUI DO Switching Test Circuit Am79C961A V THRESHOLD 19364B-32 19364B-33 ...
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SWITCHING TEST CIRCUITS TXD+ TXD– Includes Test Jig Capacitance TXP+ TXP– 294 Test Point 294 100 TXD Switching Test Circuit DV DD 715 715 100 pF Includes Test Jig Capacitance DV SS TXD Outputs Test ...
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SWITCHING WAVEFORMS: BUS MASTER MODE AEN, SBHE, SA0–9 IOW SD AEN, SBHE, SA0–9 IOW IOCHRDY SD 152 Stable t IOW1 t IOW3 t IOW5 I/O Write without Wait States Stable t IOW1 t t IOW8 IOW9 t IOW7 t IOW5 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE EESK (PRDB0) EECS EEDI (PRDB1) EEDO (PRDB2) SHFBUSY Serial Shift EEPROM Interface Read Timing EESK (PRDB0) EECS EEDI (PRDB1) SHFBSY EED0 (PRDB2 Falling ...
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SWITCHING WAVEFORMS: BUS MASTER MODE EED0 (PRDB2) IOR IOCHRDY IOW EESK, EEDI, EECS, SHFBUSY AEN, SBHE, SA0–9 IOR SD 154 t SL1 t SL2 Slave Serial EEPROM Latency Timing Stable t IOR1 t IOR5 Stable I/O Read without Wait States ...
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SWITCHING WAVEFORMS: BUS MASTER MODE AEN, SBHE, SA0–9 IOR IOCHRDY SD IOW, MEMW MEMR, IOR Stable t IOR1 t t IOR6 IOR7 t IOR8 Stable I/O Read with Wait States t IOM1 I/O to Memory Command Inactive Time Am79C961A t ...
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SWITCHING WAVEFORMS: BUS MASTER MODE AEN, SBHE, SA0–9 IOCS16 REF t MMA1 DRQ t MMA2 DACK t MMA3 MASTER MEMR/MEMW SBHE, SA0–19, LA17–23 156 t IOCS IOCS16 Timings t MMA4 t MMA5 Bus Acquisition Am79C961A t IOCS2 19364B-44 19364B-45 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE DRQ DACK MASTER MEMR/MEMW SBHE, SA0–19, LA17–23 (Non Wait) SBHE, SA0–19, LA17–23 t MMW1 MEMW IOCHRDY t MMW10 SD0– MMBR1 MMBR2 t MMBR3 t MMBR4 Bus Release (Wait States Added MMW5 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE (Non Wait) SBHE, SA0–19, Stable LA17–23 t MMR1 MEMR IOCHRDY SD0–15 AEN, SBHE, SA0–9 IOR IOCHRDY APCS (IRQ15) PRDB0–7 SD0–7 158 t t MMR6 MMR5 t t MMR3 MMR2 t t MMR11 MMR10 Stable Read ...
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SWITCHING WAVEFORMS: BUS MASTER MODE BALE LA20–23 t MB13 REF, SBHE, SA0–19 t MB1 MEMR t t MB14 IOCHRDY BPCS PRDB0–7 SD0–7 t MB12 Stable Stable MB3 t MB5 t MB6 t MB8 Boot PROM Read Cycle Am79C961A t MB2 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE BALE LA20–23 t MFR13 REF, SBHE, SA0–19 t MFR1 MEMR t t MFR14 MFR3 IOCHRDY BPCS PRDB0–7 SD0–7 160 t MFR12 Stable Stable t MFR5 t MFR6 t MFR8 Flash Read Cycle Am79C961A t MFR2 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE BALE LA20–23 t MFW14 SBHE, SA0–19 t MFW1 MEMW t t MFW15 MFW3 IOCHRDY SD0-7 FL_WE (IRQ12) PRDB0-7 t MFW13 Stable Stable t MFW7 Stable t t MFW10 MFW11 t MFW9 Stable Flash Write Cycle ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE AEN, SBHE, SA0–9 IOW SD AEN, SBHE, SA0–9 t IOW1 IOW IOCHRDY SD 162 Stable t IOW t IOW1 t IOW5 I/O Write without Wait States Stable t t IOW IOW8 t IOW9 t IOW5 ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE AEN, SBHE, SA0–9 IOR SD AEN, SBHE, SA0–9 IOR IOCHRDY SD Stable t IOR1 t IOR5 Stable I/O Write without Wait States Stable t IOR1 t t IOR6 IOR7 t IOR8 I/O Read with Wait ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE SA0–15, SBHE SMAM MEMW SD SA0–15, SBHE SMAM t MW1 MEMW IOCHRDY SD 164 Stable t MW1 t MW3 t MW5 Memory Write without Wait States Stable t MW7 t t MW9 MW8 Memory Write ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE SA0–15, SBHE SMAM MEMR SD SA0–15, SBHE SMAM/BPAM MEMR IOCHRDY SD Stable t MR1 t MR5 Stable Memory Read without Wait States Stable t MR1 t t MR7 MR6 t MR8 Memory Write with Wait ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE IOW, MEMW MEMR, IOR AEN, SBHE, SA0–9 IOCS16 166 t IOM1 I/O to Memory Command Inactive Time t IOCS1 IOCS16 Timings Am79C961A t IOM2 19364B-61 t IOCS2 19364B-62 ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE SBHE, SA0–15, BPAM t SFW1 MEMW t SFW3 IOCHRDY SD0-7 SRWE BPCS PRDB0-7 Stable t SFW7 Stable t SFW10 t SFW11 t SFW9 Stable Flash Write Cycle Am79C961A t SFW2 t SFW6 t SFR4 t ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE REF, SBHE SA0-15 t SFR1 MEMR t SFR3 IOCHRDY SROE BPCS PRDB0–7 SD0–7 168 Stable t SFR7 t SFR5 t SFR6 t t SFR8 SFR9 Flash Read Cycle Am79C961A t SFR2 t SFR4 t t ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE PRAB SRWE PRDB SRCS (IRQ12) PRAB SROE PRDB SRCS (IRQ12) SRAM Read on Private Bus (When FL_Sel is Enabled) t PR13 t PR14 t PR15 SRAM Write on Private Bus (When FL_Sel is Enabled) t ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE PRAB BPCS PRDB PRAB0–9 APCS (IRQ15) PRDB 170 t PR10 t t PR11 PR12 Boot PROM Read on Private Bus t PR7 t PR8 Address PROM Read on Private Bus Am79C961A t PR10 t t ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE PRAB0 t PR14 SRWE PRDB FLCS PRAB0 FLOE FLCS PRDB t t PR17 PR17 t PR14 t t PR18 PR18 Flash Write on Private Bus t t PR16 PR16 t t PR11 PR12 Flash Read ...
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SWITCHING WAVEFORMS: GPSI (First Bit Preamble) t GPT1 t GPT2 Transmit Clock (STDCLK) t GPT3 Transmit Data (TXDAT) t GPT3 Transmit Enable (TXEN) Carrier Present (RXCRS) (Note 1) t GPT9 Collision (CLSN) (Note 2) Notes: 1. RXCRS is not present ...
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SWITCHING WAVEFORMS: EADI SRDCLK (LED3) One Zero One SRD (LED2) t EAD1 t EAD2 SF/BD (LED1) t EAD4 EAR (MAUSEL) SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE t JTG1 TCK t t JTG3 JTG4 TDI t JTG5 TMS TDO Preamble SFD ...
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SWITCHING WAVEFORMS: AUI XTAL1 t ISTDCLK XI (Note 1) ITXEN (Note 1) 1 ITXDAT+ (Note 1) DO+ DO– DO Note: 1. Internal signal and is shown for clarification only. 174 DOTR 1 Transmit Timing—Start of Packet Am79C961A ...
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SWITCHING WAVEFORMS: AUI XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ (Note 1) DO+ DO– Bit (n–2) Transmit Timing—End of Packet (Last Bit = 0) Note: 1. Internal signal and is shown for clarification only. 0 ...
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SWITCHING WAVEFORMS: AUI XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ (Note 1) DO+ DO– Bit (n–2) Transmit Timing—End of Packet (Last Bit = 1) Note: 1. Internal signal and is shown for clarification only. 176 ...
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SWITCHING WAVEFORMS: AUI DI+/– V ASQ t PWKDI t PWODI CI+/– V ASQ t PWOCI t DO+/– Receive Timing Diagram PWKCI Collision Timing Diagram t DOETD 40 mV 100 mV max. 80 Bit Times Port DO ETD Waveform Am79C961A t ...
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SWITCHING WAVEFORMS: 10BASE-T INTERFACE TXD+ TXP+ TXD– TXP– XMT (Note 1) Note: 1. Internal signal and is shown for clarification only. t PWPLP TXD+ TXP+ TXD– TXP– t PWLP 178 Transmit Timing t PERLP Idle Link ...
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SWITCHING WAVEFORMS: 10BASE-T INTERFACE RXD Receive Thresholds (LRT = 0 in CSR15 bit 9) RXD Receive Thresholds (LRT = 1 in CSR15 bit 9) V THS+ V THS– V LTHS+ V LTHS– Am79C961A V TSQ+ V TSQ– 19364B-83 V LTSQ+ ...
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PHYSICAL DIMENSIONS* PQB132 Plastic Quad Flat Pack Trimmed and Formed (measured in inches) Pin 33 Pin 33 180 1.097 1.097 1.103 1.103 1.075 1.075 1.085 1.085 0.947 0.947 0.953 0.953 Pin 132 Pin 132 Pin 1 I.D. Pin 1 I.D. ...
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PHYSICAL DIMENSIONS* PQB132 Molded Carrier Ring Plastic Quad Flat Pack (measured in inches, Ring measured in millimeters) Z1 1.50 DIA. 45.87 46.13 45.50 45.90 32.15 41.37 32.25 41.63 1.097 1.103 37.87 .944 38.13 .952 35.15 35.25 1.50 DIA. 1.80 45.87 ...
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APPENDIX A PCnet-ISA II Compatible Media Interface Modules PCnet-ISA II COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS The table below provides a sample list of PCnet-ISA II compatible 10BASE-T filter and transformer modules Manufacturer Part No. Bel Fuse A556-2006-DE 16-pin 0.3" DIL ...
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PCnet-ISA II Compatible DC/DC Converters The table below provides a sample list of PCnet-ISA II compatible DC/DC converters available from various Manufacturer Part No. Halo Electronics DCU0-0509D Halo Electronics DCU0-0509E PCA Electronics EPC1007P PCA Electronics EPC1054P PCA Electronics EPC1078 Valor ...
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APPENDIX B Layout Recommendations for Reducing Noise DECOUPLING LOW-PASS R/C FILTER DESIGN The PCnet-ISA II controller is an integrated, single-chip Ethernet controller, which contains both digital and analog circuitry. The analog circuitry contains a high speed Phase-Locked Loop (PLL) and ...
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V Plane 6 DD2 Pin 108 AV SS2 Pin PCnet-ISA II To determine the value for the resistor and capacitor, the formula is Where R ...
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APPENDIX C Sample Plug and Play Configuration Record SAMPLE CONFIGURATION FILE The following is a sample configuration record for the PCnet-ISA II device used in an AMD Ethernet card. This card requires one DMA channel, one interrupt, one I/O port ...
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Logical Device ID ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; DB 0x15 DB 0x04 DB 0x96 DB 0x55 DB 0xAA DB 0x02 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Compatible Device ID ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; DB 0x1C DB 0x41 DB 0xD0 DB 0x82 DB 0x8C ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; I/O Port Descriptor ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ...
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APPENDIX D Alternative Method for Initialization The PCnet-ISA II controller may be initialized by performing I/O writes only. That is, data can be written directly to the appropriate control and status registers (CSR) instead of reading from the Initialization Block ...
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APPENDIX E Introduction of the Look- Ahead Packet Processing (LAPP) Concept A driver for the PCnet-ISA II controller would normally require that the CPU copy receive frame data from the controller’s buffer space to the application’s buffer space after the ...
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Note: The labels in the following text are used as references in the timeline diagram that follows. SETUP: The driver should set up descriptors in groups of 3, with the OWN and STP bits of each set of three descriptors ...
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S6: After the ownership of descriptor number 2 has been changed by the PCnet-ISA II controller, the next driver poll of the 2nd descriptor will show ownership granted to the CPU. The driver now copies the data from buffer number ...
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LAPP Enable Software Requirements Software needs to set up a receive ring with descriptors formed into groups of 3. The first descriptor of each group should have OWN = 1 and STP = 1, the second descriptor of each group ...
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The controller will discard all descriptors with OWN = 1 and STP = 0 and move to the next descriptor when searching for a place to begin a new frame. It dis- cards these desciptors by simply changing the owner- ...
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Assume that instead of the expected 1060 byte frame, a 100 byte frame arrives, because there was an error in the network, or because this is the last frame in a file transmission sequence, or perhaps because it is ...
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S5 and S7 as such: While the driver is polling for each descriptor, it could count the number of poll oper- ations performed and then adjust the number 1 buffer ...
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Ethernet Wire activity: } C10: ERP interrupt is generated. C9: Controller writes descriptor #3. C8: Controller is performing intermittent bursts of DMA to fill data buffer #3. N2:EOM C7: Controller writes descriptor #2. C6: "Last chance" lookahead to descriptor #3 ...
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OWN = 1 Descriptor SIZE = HEADER_SIZE (minimum 64 bytes) #1 OWN = 1 STP = 0 Descriptor SIZE = S1+S2+S3+S4 #2 OWN = 0 STP = 0 Descriptor SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE) #3 OWN = 1 STP = ...
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