AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 75

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

External Clock Drive Characteristics
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than 0.5 ns jitter at DO .
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO ) are
designed to operate into terminated transmission lines.
When operating into a 78
line, the transmit signaling meets the required output
levels and skew for Cheaper net, Ethernet, and
IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental-mode crystal oscillator pro-
vides the basic timing reference for the MENDEC por-
tion of the PCnet-ISA II controller. The crystal input is
divided by two to create the internal transmit clock ref-
erence. Both clocks are fed into the Manchester
Encoder to generate the transitions in the encoded
data stream. The internal transmit clock is used by the
MENDEC to internally synchronize the Internal Trans-
mit Data (ITXDAT) from the controller and Internal
Transmit Enable (ITXEN). The internal transmit clock is
also used as a stable bit-rate clock by the receive sec-
tion of the MENDEC and controller.
The oscillator requires an external 0.005% crystal, or
an external 0.01% CMOS-level input as a reference.
The accuracy requirements, if an external crystal is
used, are tighter because allowance for the on-chip
oscillator must be made to deliver a final accuracy of
0.01%.
Transmission is enabled by the controller. As long as
the ITXEN request remains active, the serial output of
the controller will be Manchester encoded and appear
at DO . When the internal request is dropped by the
controller, the differential transmit outputs go to one of
two idle states, dependent on TSEL in the Mode
Register (CSR15, bit 9):
TSEL LOW:
TSEL HIGH:
Clock Frequency:
Rise/Fall Time (tR/tF):
XTAL1 HIGH/LOW Time
(tHIGH/tLOW):
XTAL1 Falling Edge to
Falling Edge Jitter:
The idle state of DO yields “zero”
differential to operate transformer-coupled
loads
In this idle state, DO+ is positive with respect
to DO– (logical HIGH).
20 MHz 0.01%
< 6 ns from 0.5 V to V
40 – 60% duty cycle
< 0.2 ns at 2.5 V input (VDD/2)
terminated transmission
DD
–0.5
Am79C961A
Receive Path
The principal functions of the receiver are to signal the
PCnet-ISA II controller that there is information on the
receive pair, and to separate the incoming Manchester
encoded data stream into clock and NRZ data.
The receiver section (see Receiver Block Diagram)
consists of two parallel paths. The receive data path is
a zero threshold, wide bandwidth line receiver. The
carrier path is an offset threshold bandpass detecting
line receiver. Both receivers share common bias
networks to allow operation over a wide input common
mode range.
Input Signal Conditioning
Transient noise pulses at the input data stream are
rejected by the Noise Rejection Filter. Pulse width
rejection is proportional to transmit data rate which is
fixed at 10 MHz for Ethernet systems but which could
be different for proprietary networks. DC inputs more
negative than minus 100 mV are also suppressed.
The Carrier Detection circuitry detects the presence of
an incoming data packet by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock
acquisition. Clock acquisition requires a valid
Manchester bit pattern of 1010b to lock onto the incom-
ing message.
When input amplitude and pulse width conditions are
met at DI , a clock acquisition cycle is initiated.
Clock Acquisition
When there is no activity at DI (receiver is idle), the
receive oscillator is phase-locked to STDCLK. The first
negative clock transition (bit cell center of first valid
Manchester “0") after clock acquisition begins inter-
rupts the receive oscillator. The oscillator is then
restarted at the second Manchester “0" (bit time 4) and
is phase-locked to it. As a result, the MENDEC
acquires the clock from the incoming Manchester bit
pattern in 4 bit times with a “1010" Manchester bit pat-
tern.
The internal receiver clock, IRXCLK, and the internal
received data, IRXDAT, are enabled 1/4 bit time after
clock acquisition in bit cell 5. IRXDAT is at a HIGH state
when the receiver is idle (no IRXCLK). IRXDAT how-
ever, is undefined when clock is acquired and may
remain HIGH or change to LOW state whenever IRX-
CLK is enabled. At 1/4 bit time through bit cell 5, the
controller portion of the PCnet-ISA II controller sees the
first IRXCLK transition. This also strobes in the
incoming fifth bit to the MENDEC as Manchester “1".
IRXDAT may make a transition after the IRXCLK rising
edge in bit cell 5, but its state is still undefined. The
Manchester “1" at bit 5 is clocked to IRXDAT output at
1/4 bit time in bit cell 6.
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